Patents Assigned to Agate Logic, Inc.
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Method for selectively establishing an electrical connection in a multi-terminal phase change device
Patent number: 8178380Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.Type: GrantFiled: July 9, 2009Date of Patent: May 15, 2012Assignee: Agate Logic, Inc.Inventors: Louis Charles Kordus, II, Antonietta Oliva, Narbeh Derharcobian, Vei-Han Chan -
Patent number: 8131909Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.Type: GrantFiled: September 19, 2007Date of Patent: March 6, 2012Assignee: Agate Logic, Inc.Inventors: Hare Krishna Verma, Manoj Gunwani, Ravi Sunkavalli
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Publication number: 20110317720Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.Type: ApplicationFiled: September 6, 2011Publication date: December 29, 2011Applicant: Agate Logic, Inc.Inventors: Malcolm J. Wing, Jay B. Patel, Jeffrey M. Schroeder
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Patent number: 8063455Abstract: A multi-terminal electromechanical nanoscopic switching device which may be used as a memory device, a pass gate, a transmission gate, or a multiplexer, among other things.Type: GrantFiled: November 22, 2005Date of Patent: November 22, 2011Assignee: Agate Logic, Inc.Inventors: Louis Charles Kordus, II, Colin Neal Murphy, Malcolm John Wing
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Patent number: 8049531Abstract: A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general purpose IO block in a heterogeneous configurable integrated circuit (HCIC).Type: GrantFiled: September 14, 2007Date of Patent: November 1, 2011Assignee: Agate Logic, Inc.Inventors: Jason Golbus, Colin N. Murphy, Alexander D. Taylor
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Patent number: 8050262Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.Type: GrantFiled: July 5, 2010Date of Patent: November 1, 2011Assignee: Agate Logic, IncInventors: Malcolm J. Wing, Jay B. Patel, Jeffrey M. Schroeder
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Patent number: 7970979Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.Type: GrantFiled: September 19, 2007Date of Patent: June 28, 2011Assignee: Agate Logic, Inc.Inventors: Hare Krishna Verma, Manoj Gunwani, Ravi Sunkavalli
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Publication number: 20110122686Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.Type: ApplicationFiled: December 21, 2010Publication date: May 26, 2011Applicant: AGATE LOGIC, INC.Inventors: David Richard Trossen, Malcolm John Wing
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Patent number: 7944236Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.Type: GrantFiled: August 12, 2010Date of Patent: May 17, 2011Assignee: Agate Logic, Inc.Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
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Patent number: 7940557Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.Type: GrantFiled: December 21, 2010Date of Patent: May 10, 2011Assignee: Agate Logic, Inc.Inventors: David Richard Trossen, Malcolm John Wing
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Patent number: 7902862Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.Type: GrantFiled: September 14, 2007Date of Patent: March 8, 2011Assignee: Agate Logic, Inc.Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
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Patent number: 7889530Abstract: A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM).Type: GrantFiled: September 14, 2007Date of Patent: February 15, 2011Assignee: Agate Logic Inc.Inventors: Robert Yu, Dave Trossen, Jack Liu, Mukunda Krishnappa, Kevin James
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Patent number: 7885103Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.Type: GrantFiled: November 22, 2005Date of Patent: February 8, 2011Assignee: Agate Logic, Inc.Inventors: David Richard Trossen, Malcolm John Wing
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Publication number: 20110010406Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.Type: ApplicationFiled: September 17, 2010Publication date: January 13, 2011Applicant: AGATE LOGIC, INC.Inventors: Hare K. Verma, Ravi Sunkavalli, Manoj Gunwani
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Publication number: 20100306429Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.Type: ApplicationFiled: August 12, 2010Publication date: December 2, 2010Applicant: AGATE LOGIC, INC.Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
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Patent number: 7836113Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.Type: GrantFiled: October 9, 2006Date of Patent: November 16, 2010Assignee: Agate Logic, Inc.Inventors: Ravi Sunkavalli, Hare K. Verma, Manoj Gunwani, Elliott Delaye
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Patent number: 7814136Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.Type: GrantFiled: February 1, 2006Date of Patent: October 12, 2010Assignee: Agate Logic, Inc.Inventors: Hare K. Verma, Ravi Sunkavalli, Manoj Gunwani
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Patent number: 7786757Abstract: Methods for interconnecting base, switching and interconnect resources for configurable integrated circuits are provided, where these methods include the following steps: interconnecting base and switching resources with interconnect resources to form a hierarchical interconnect structure; physically placing the hierarchical interconnect structure in a two dimensional format; and directly interconnecting selected neighboring base and switching resources. The integrated circuits generated include base resources, interconnect resources; and switching resources that are interconnected to form a hierarchical interconnect structure, and, additional interconnect resources that directly interconnect neighboring switching or base resources.Type: GrantFiled: March 21, 2008Date of Patent: August 31, 2010Assignee: Agate Logic, Inc.Inventors: Ernst Mayer, Ronald H. Nicholson, Jr., Steven Winegarden
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Patent number: 7773595Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.Type: GrantFiled: September 14, 2007Date of Patent: August 10, 2010Assignee: Agate Logic, Inc.Inventors: Malcolm J. Wing, Jay B. Patel, Jeffrey M. Schroeder
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Patent number: 7757193Abstract: A method for clustering logic units in a field programmable integrated chip to generate a set of clusters is disclosed. The clustering step for forming a super cluster comprises a first logic element and a second logic unit a first logic unit and a super cluster, or a first super cluster and a second super cluster. The method includes generating all possible configurations by enumerating all possible two-way relationships combining a driver-and-receiver relationship from a pool of a finite number of dedicated connections. The set of all possible configurations is reduced to a subset of configurations based on one or more multi-dimension criteria. Each dimension in the multi-dimensional criteria is represented by a parameter. The method involves prioritizing a collection of parameters so that a set of selected parameters or a set of selected criteria is used to generate a desirable number of subsets of configurations.Type: GrantFiled: October 2, 2006Date of Patent: July 13, 2010Assignee: Agate Logic, Inc.Inventor: Bo Hu