Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

Abstract: An integrated circuit memory system and method for precision hot carrier injection programming of single or plurality of nonvolatile memory cells is described. Each program cycle is followed by a verify cycle. Precision programming is achieved by incrementally changing a programming current pulse flowing between the source and drain in the memory cell during successive program cycles and a constant current during successive verify cycles. Current control and voltage mode sensing circuitry reduces circuit complexity, reduces programming cell current, lowers power dissipation, and enables page mode operation. Precision programming is useful for multilevel digital and analog information storage.

Abstract: An integrated circuit storing multiple bits per memory cell is described. The amount of charge stored in a memory cell corresponds the multiple bits in a memory cell. Dual banks of shift registers are alternately coupled to one or more data pins and to the memory cells of the memory array speed data transfer for reading and writing operation. Reading is performed in the voltage mode to conserve power. During writing operations, reading of a memory cell is performed in the voltage mode to determine whether the desired programming of the memory cell has been achieved. During the reading of a memory cell, the voltage corresponding to the amount of charge stored in a memory cell is compared against a binary search sequence of reference voltages to determine the multiple bits stored in the memory cell.

Abstract: An integrated circuit memory system having memory cells capable of storing multiple bits per memory cell is described. The memory system has a restoring operation in which a memory cells' stored charge, which may drift from its initially set condition, is maintained within one of a plurality of predetermined levels corresponding to digital bits of information and defined by a set of special reference voltage values. The memory system has mini-programming and mini-erasing operations to move only the amount of charge into and out of the memory cell sufficient to keep the charge within the predetermined levels. The memory system also has an operation for high speed programming of the memory cells and an erasing operation to narrow the charge distribution of erased memory cells for increasing the spread, and safety margins, between the predetermined levels.

Abstract: An integrated circuit memory system and method for precision hot carrier injection programming of single or plurality of nonvolatile memory cells is described. Each program cycle is followed by a verify cycle. Precision programming is achieved by incrementally changing a programming current pulse flowing between the source and drain in the memory cell during successive program cycles and a constant current during successive verify cycles. Current control and voltage mode sensing circuitry reduces circuit complexity, reduces programming cell current, lowers power dissipation, and enables page mode operation. Precision programming is useful for multilevel digital and analog information storage.

Abstract: An integrated circuit memory system having memory cells capable of storing multiple bits per cell is described. The memory system has a restoring operation in which a memory cells' stored charge, which may drift from its initially set condition, is maintained within one of a plurality of predetermined levels corresponding to digital bits of information and defined by a set of special reference voltage values. The memory system has mini-programming and mini-erasing operations to move only the amount of charge into and out of the memory cell sufficient to keep the charge within the predetermined levels. The memory system also has an operation for high speed programming of the memory cells and an erasing operation to narrow the charge distribution of erased memory cells for increasing the spread, and safety margins, between the predetermined levels.

Abstract: An integrated circuit storing multiple bits per memory cell is described. The amount of charge stored in a memory cell corresponds the multiple bits in a memory cell. Dual banks of shift registers are alternately coupled to one or more data pins and to the memory cells of the memory array speed data transfer for reading and writing operation. Reading is performed in the voltage mode to conserve power. During writing operations, reading of a memory cell is performed in the voltage mode to determine whether the desired programming of the memory cell has been achieved. During the reading of a memory cell, the voltage corresponding to the amount of charge stored in a memory cell is compared against a binary search sequence of reference voltages to determine the multiple bits stored in the memory cell.