Abstract: A method of providing a reference voltage for reading of a resistive memory array, and a read circuit for reading of a resistive memory array. The method comprises the steps of generating a first reference voltage when a bitline of the resistive memory array is in a first resistance state, and generating a second reference voltage when the bitline is in a second resistance state; wherein the first reference voltage is different from the first reference voltage and the first resistance state is different from the second resistance state.
Type:
Grant
Filed:
December 28, 2018
Date of Patent:
July 7, 2020
Assignees:
NATIONAL UNIVERSITY OF SINGAPORE, AGENCY FPR SCIENCE, TECHNOLOGY AND RESEARCH
Inventors:
Kien Trinh Quang, Massimo Alioto, Sergio Ruocco