Abstract: A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit.
Type:
Grant
Filed:
December 23, 2003
Date of Patent:
May 15, 2007
Assignee:
Agere Syatems Inc.
Inventors:
Dipankar Bhattacharya, Makeshwar Kothandaraman, John Christopher Kriz, Bernard Lee Morris, Jeffrey Jay Nagy, Stefan Allen Siegel