Abstract: Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes a digital filter that receives a series of digital samples and provides a filtered output. The filtered output is provided to a data detector that performs a data detection on the filtered output to create a detected output. A first summation element subtracts the filtered output from the detected output to create an error signal, and a second summation element subtracts the error signal from the filtered output to create a wander basis signal. A baseline correction feedback circuit receives the wander basis signal and provides a wander compensation signal. A derivative of the wander compensation signal is provided as feedback to the digital filter.

Abstract: In one embodiment, an apparatus comprising a housing and a fastener, such as a clip (101, 201) for fastening the apparatus (100, 200) to an article of clothing. The housing (102, 202) has a recess (103, 203) formed therein, such that at least a portion of the fastener is adapted to fit within the recess. The fastener is adapted to travel slidably within the recess (103, 203) between a first position in which the fastener enables the apparatus (100, 200) to be fastened to an external object and a second position in which the fastener is stowed away.

Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.

Abstract: A network device comprises a plurality of lookup tables and a processor. Each of the plurality of lookup tables comprises a plurality of table inputs that are associated with a plurality of processor instructions. The processor is operative to perform a network operation on a packet of data comprising a plurality of protocol header fields at least in part by performing one or more lookup cycles. A lookup cycle comprises the addressing of one of the plurality of lookup tables with one of the plurality of table inputs and the performing of the processor instruction associated with that table input. At least one of the plurality of processor instructions in the plurality of lookup tables comprises an instruction directing that the content of one of the plurality of protocol header fields be read and that one of the plurality of lookup tables be addressed with that content as the table input.

Abstract: An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test bus between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies.

Abstract: In one embodiment, defects are detected on the face of a hard-disk drive platter. A preamble, a sync mark, user or pseudorandom data, and a data pad are written to every sector on a track of the platter. Inter-sector gaps that separate consecutive sectors are overwritten with a fixed data pattern such that consecutive sectors are in phase lock with one another. After the track has been written, the track is read back and analyzed. Consecutive sectors are analyzed continuously without stopping. The preambles, sync marks, data pads, and overwritten inter-sector gaps are analyzed using suitable flaw-scan techniques. The user or pseudorandom data is analyzed using both data-integrity checks and suitable flaw-scan techniques. This process is repeated for all tracks on the disk, and defect detection is completed when all tracks have been analyzed.

Abstract: A method and apparatus for improving the thermal conductivity of a circuit board (CB) assembly comprising an integrated circuit (IC) die mounted on a CB. A high thermal conductivity device is attached on a first end to a surface of the die. When the die is mounted on the CB, a void formed in the CB receives a second end of the HTC device, and the second end of the HTC device comes into contact with a portion of the CB. During operation of the die, heat produced by the die is dissipated through the HTC device and into the CB.

Abstract: A dedicated wireless data connection to the Internet through which digital broadcasts are streamed to mobile devices specifically designed to receive and play the content of the broadcasts. A user is supplied with a hand-held mobile terminal device specifically designed for the reception and playback of Internet radio wirelessly and the content available to the user of the device is automatically pre-specified based upon the connection node with which the device is currently communicating. The device creates and maintains a wireless connection to the Internet through any existing access technology (e.g., cellular or Wi-Fi access technology), manages the connection, including roaming, and buffers data in order to present a continuous stream of content to the end-user. Using this model, local advertisers and/or stations can pay the wireless service provider to have their content broadcast in a particular region, thereby enabling regional advertising to be delivered to listeners.

Abstract: Various embodiments of the present invention provide systems and methods for performing modified rate burst demodulation. For example, a method for performing modified rate burst demodulation is disclosed. The method includes receiving a data input that includes a synchronization pattern, an information pattern, and a demodulation pattern. A periodic boundary is established along with a phase and frequency of a sampling clock based at least in part on the synchronization pattern. The information pattern is processed using the sampling clock to determine a location fix. The sampling clock is phase shifted by a skew amount and a phase shifted sampling clock is provided. The demodulation pattern is processed using the phase shifted sampling clock.

Abstract: A method is disclosed for controlling the flow of packets aggregated from multiple logical ports over a transport link. A directed flow control indicator is provided to the transmitting end station that causes a detected congestion condition. The directed flow control indicator causes the transmitting end station to suspend the transmission of further packets. The linear expansion header of the Generic Framing Procedure (GFP) linear mapping scheme is extended to include the flow control indicator, such as a bit indicating a potential overload condition. A directed flow control indication can be provided in one or more packets sent to the transmitting end station over the transport network without increasing the network overhead. If packets are not being sent to the appropriate transmitting end station, a packet generator can generate one or more packets with the flow control indicator to inform the appropriate transmitting end station of the congestion condition.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

Abstract: In one embodiment, a receiver has an equalizer, a tap-averaging block, a delay buffer, and a filter. The equalizer receives an input signal from upstream processing and generates sets of filter coefficients. Each set of filter coefficients is adaptively generated by 1) filtering the received signal to generate an equalized signal, 2) calculating an error of the equalized signal, and 3) generating a new set of coefficients based on the error of the equalized signal. The sets of filter coefficients are output to the tap-averaging block, which averages groups of the sets of filter coefficients to generate sets of averaged filter coefficients, where each averaged set is output to the filter. The filter receives a time-delayed version of the input signal from the delay buffer and applies the current set of averaged filter coefficients to the time-delayed signal. The filtered signal is then output to downstream processing.

Abstract: A secondary satellite radio or broadcast channel is used to broadcast advertisement clips (e.g., audio clips) to a receiver for subsequent decoding and playback. The receiver is configured for different tiers of service, e.g., one that delivers substantially advertising-free content and another that delivers content that includes more significant amounts of advertising. The content delivered to both is the same content; however, for the service tier that includes more advertising, the advertisements broadcast on the secondary channel are interleaved into the content, preferably in such a way that the continuity of the content being delivered is not compromised.

Abstract: A method for extending a tracking range of a PLL includes the steps of: establishing an initial tracking window of the PLL, the tracking window having a first width associated therewith; and dynamically adjusting the tracking window of the PLL within an extended tracking range when a frequency of an input signal supplied to the PLL is outside of the tracking window, the extended tracking range having a second width associated therewith which is greater than the first width.

Abstract: An improved multi-channel receiver for satellite broadcast applications or the like. In an exemplary embodiment, an AGC loop, under the control of an AGC processor, controls the gain of an analog sub-receiver adapted to simultaneously receive multiple signals to achieve a desired AGC setpoint signal intensity from the sub-receiver. Multiple digital demodulators, coupled to the sub-receiver by an analog-to-digital converter (ADC), demodulate the multiple received signals. The AGC controller, based upon which of the received signals are being demodulated, selects the desired AGC setpoint from a table of setpoints. The AGC controller may also provide selective power control to circuitry in the receiver and select the resolution of the ADC. The controller updates the AGC loop with step values selected from a group of values by an AGC control algorithm. Different groups of step values may be used by the controller depending on whether the signals are fading or not.

Abstract: Embodiments of the invention include a temperature sensor method for providing an output voltage response that is linear to the temperature of the integrated circuit to which the temperature sensor belongs and/or the integrated circuit die on which the temperature sensor resides. The output voltage of the temperature sensor has an adjustable gain component and an adjustable voltage offset component that both are adjustable independently based on circuit parameters. The inventive temperature sensor includes an offset circuit that diverts a portion of current from the scaled PTAT current before the current is sourced through the output resistor. The offset circuit includes a bandgap circuit arrangement, a voltage to current converter arrangement, and a current mirror arrangement that are configured to provide a voltage offset adjustable based on independent circuit parameters such as resistor value ratios and transistor device scaling ratios.

Abstract: An apparatus for transporting data in a network-based data communication system includes a first network node comprising a first port couplable to at least a second network node for transferring data in a first format between the first and second network nodes. The first network node further includes a processor operatively coupled to the first port, the processor being configurable to receive one or more frames of data and/or transmit one or more frames of data, the frames of data having an overhead processing portion that is otherwise standard. The processor uses only a subset of the overhead processing portion and is configured such that utilizing only the subset of the overhead processing portion of the one or more data frames enables one or more functional blocks to be eliminated from the first network node, the one or more functional blocks being otherwise required for implementing substantially all of the overhead processing portion of the one or more data frames.

Abstract: In one embodiment, a timing-offset estimator calculates a correlation value for each sample of an OFDM signal having a cyclic prefix for each OFDM symbol. The correlation value is provided to a tapped delay line that applies a separate weight to each of 2V correlation values, where V is the length of the cyclic prefix and the weights are based on a triangular weighting scheme that increases linearly from the first value, peaks at the Vth value, and decreases linearly to the 2Vth value. A stream of combined, squared correlation values is generated by combining and squaring the 2V weighted correlation values for each sample of the OFDM signal. For each cyclic prefix of the OFDM signal, a timing-offset estimate is determined based on a detected peak value in the stream of combined, squared correlation values. A timing-offset estimator with triangular weighting scheme may be implemented using recursive processing.

Abstract: Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.

Abstract: The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.