Abstract: A method and apparatus are disclosed for detecting the removal of a device connected to a network. The present invention generates an alarm on a protected device when an unauthorized user disconnects the device from a network connection. The network connection is monitored and an alarm is generated if the protected device is disconnected from the network connection without proper notification to the theft protection utility. A number of fail-safe features can optionally be employed to ensure that the theft protection aspects of the present invention are not bypassed. For example, the theft protection utility process can employ speaker, volume and/or power control features to ensure that the alarms generated by the present invention, or the theft protection feature itself, cannot be bypassed.

Abstract: Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft-output detector is provided for processing a received signal, comprising: a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states. A method is provided for processing a received signal using a soft-output detector, comprising: calculating forward state metrics using a forward detector; calculating backward state metrics using a backward detector; and calculating a current branch metric using a current branch detector, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states.

Abstract: Techniques for processing power transistor devices are provided. In one aspect, the curvature of a power transistor device comprising a device film formed on a substrate is controlled by thinning the substrate, the device having an overall residual stress attributable at least in part to the thinning step, and applying a stress compensation layer to a surface of the device film, the stress compensation layer having a tensile stress sufficient to counterbalance at least a portion of the overall residual stress of the device. The resultant power transistor device may be part of an integrated circuit.

Abstract: Generally, a method and apparatus are disclosed that store sequential data units of a data packet received at an input port in contiguous banks of a buffer in a shared memory, thereby obviating any need for storing linkage information between data units. Data packets can extend through multiple buffers (next-buffer linkage information is much more efficient than next-data-unit linkage information). According to another aspect of the invention, buffer memory utilization can be further enhanced by storing multiple packets in a single buffer. For each buffer, a buffer usage count is stored that indicates the sum (over all packets represented in the buffer) of the number of output ports toward which each of the packets is destined.

Abstract: Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for evaluating the quality of a data eye associated with a signal. The received signal is sampled for a plurality of different phases, for example, using at least two latches, and the samples are evaluated to identify when the signal crosses a predefined amplitude value, such as a zero crossing. It is determined whether the points of predefined amplitude crossing satisfy one or more predefined criteria. One or more parameters of one or more channel compensation techniques can optionally be adjusted based on a result of the determining step. One or more parameters of an adjacent transmitter can also be adjusted to reduce near end cross talk based on a result of the determining step.

Abstract: A method of forming an electronic device, comprising providing a semiconductor substrate having a first contact and an undoped electroplated lead-free solder bump formed on the first contact. The method also comprises providing a device package substrate having a second contact and a doped lead-free solder layer on the second contact comprising a fourth row transition metal dopant. The method further comprises melting the solder bump and the solder layer while the solder layer and the solder bump are in contact, thereby forming a doped solder bump consisting essentially of Sn, one or both of Ag and Cu, and the fourth row transition metal dopant.

Abstract: In one embodiment, an algorithm dynamically selects a method for reducing distortion in a multi-carrier modulated signal, such as an orthogonal frequency division multiplexing (OFDM) signal. The algorithm directs a transmitter to transmit peak-to-average power ratio (PAPR)-reduction signals over reserved tones (i.e., frequencies) if reserved tones are available. If reserved tones are not available, then the algorithm directs the transmitter to transmit PAPR-reduction symbols over free tones if free tones are available. If the free tones for this transmitter are used by adjacent transmitters, then interference-reduction techniques may be used to reduce interference with the adjacent transmitters. If reserved tones and free tones are not available, then the transmitter may use an alternative method to reduce distortion, such as successive clipping and filtering. In another embodiment, the transmitter may transmit PAPR-reduction symbols over both free and reserved tones, if available.

Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ?? rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.

Abstract: A method of operating a communications circuit with at least one control channel and at least one data channel includes the steps of monitoring the at least one control channel, powering a receiver portion of the circuit when the at least one control channel indicates that data is to be received, and refraining from powering the receiver portion when the at least one control channel indicates that data is not to be received. The circuit can operate, for example, under the 3GPP HSDPA standard. Where desired, the clock and power supply to the receiver portion and a bit rate processing portion can be independently gated.

Abstract: A method and system for launching multiple applications simultaneously on a device under the control of application switching framework so that the operating system is only running one task for all the applications is provided. A single task is run under the control of an operating system. An application manager is run within the task. One or more applications are launched within the task under the control of the application manager. One of the applications is made the current application by switching, under user control, among the launched applications. A list of application descriptors is maintained for all the launched applications, and when switching, the application descriptor of one of the applications is used for displaying the application to a user on a screen. Each application descriptor contains forms of the launched applications. Each of the application descriptors contains a tree of forms with one root or parent form. A form represents an image to be displayed to the user.

Abstract: Apparatus and method to allow retrieval of voice messages deleted from the voice message memory of a voice messaging system. A voice messaging system such as a telephone answering device includes a deleted voice message memory for storing voice messages deleted from the voice message memory. The deleted voice messages stored in the deleted voice message memory are retrievable by the user for review subject to rules for permanent deletion of the deleted voice messages (e.g., after a period of time, when the deleted voice message memory approaches capacity, periodically, etc.).

Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.

Abstract: A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.

Abstract: Multi-dimensional finite impulse response filters ale disclosed in hybrid and transpose forms. Multi-dimensional signals can be expressed in a vector (ox matrix) form to allow multi-dimensional signals to be processed collectively. Known hybrid and transpose FIR filters are extended to the multi-dimensional case to allow multi-dimensional signals to be processed with reduced redundancies. The input signals are vectors with multidimensional components. The disclosed FIR filters include multipliers that perform matrix multiplications with multiple coefficients, and adders for performing vector additions with multiple inputs and outputs. The z-transforms are provided for the disclosed hybrid and transpose multi-dimensional FIR filters.

Abstract: Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.

Abstract: In one embodiment, a low cost, simple circuit for detecting an off-hook condition of a telecommunication line comprising tip and ring signal lines is provided. The circuit comprises a voltage divider for coupling between the tip and ring lines without an intervening transistor and having a node at which is presented a scaled version of a voltage across the voltage divider. The circuit further comprises a transistor having a control terminal coupled to the node, a first current flow terminal coupled to a voltage source, and a second current flow terminal coupled to an output terminal, wherein the output terminal bears a value that is indicative of a voltage across the tip and ring lines and thus whether the telecommunication line is off-hook.

Abstract: A network or other type of processor operates to switch packets from an incoming cell stream to an outgoing cell stream. Each received and transmitted cell in a cell stream includes portions of packets, or complete packets or both. Packets are reassembled from incoming cells, and outgoing cells may be created from portions of packets, complete packets or both. The packets in the outgoing cells may be from incoming packets, switched reassembled packets or both. Each incoming and outgoing cell is associated with one virtual channel, and each virtual channel for an outgoing cell may be different from the virtual channel corresponding to the incoming cell or cells from which a packet was reassembled. Switched packets also may have their conversation identifications changed. Partial packets or partial cells that are awaiting completion are retained such that switching capabilities associated with the virtual channel and channel identification modifications may be used.

Abstract: An electronic device, comprising a semiconductor substrate having a first metal pad formed thereover, a device package substrate having a second metal pad formed thereover, and, a doped solder bump. The doped solder bump is located between and in contact with said first and second metal pads. The doped solder bump consisting of Sn, one or both of Ag and Cu, and a fourth row transition metal dopant in a concentration range from 0.35 wt. % to 2 wt. %.

Abstract: A packet processing system comprises first processing circuitry for performing a first function, and first memory circuitry coupled to the first processing circuitry for storing received packets, wherein at least a portion of the packets stored by the first memory circuitry are usable by the first processing circuitry in accordance with the first function. The packet processing system further comprises at least second processing circuitry for performing a second function, and at least second memory circuitry coupled to the second processing circuitry for storing at least a portion of the same packets stored in the first memory circuitry, wherein at least a portion of the packets stored in the second memory circuitry are usable by the second processing circuitry in accordance with the second function. In an illustrative embodiment, the first processing circuitry and the second processing circuitry operate in a packet switching device such as a router.

Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.