Patents Assigned to AGIGA Tech
  • Patent number: 10637271
    Abstract: Disclosed herein are systems and techniques for adaptive capacitor charge voltage management, particularly for lithium-ion capacitors and hybrid capacitors. The techniques adapt the capacitor charge voltage and hence the capacitor stored energy based on capacitor operating temperature and one or more of the capacitance and the equivalent series resistance (ESR) of the capacitor.
    Type: Grant
    Filed: September 30, 2018
    Date of Patent: April 28, 2020
    Assignee: AgigA Tech
    Inventors: Ying Cai, Ronald Sartore
  • Patent number: 8650363
    Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
    Type: Grant
    Filed: May 27, 2012
    Date of Patent: February 11, 2014
    Assignee: AgigA Tech
    Inventor: Ronald H Sartore
  • Patent number: 8479061
    Abstract: A memory cartridge is described that includes a non-volatile memory. The cartridge also includes logic to concentrate memory operations on particular areas of the non-volatile memory to cause the areas of concentration to wear out at an accelerated rate relative to non areas of concentration, and logic to track wear on the non-volatile memory resulting from one or both of erases and writes.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: July 2, 2013
    Assignee: AgigA Tech
    Inventor: Ronald H Sartore
  • Patent number: 8046546
    Abstract: A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: October 25, 2011
    Assignee: AGIGA Tech
    Inventor: Ronald H Sartore