Abstract: A power module for a computer system includes an internal source of stored energy and a group of interface ports, including a management port and non-management ports. The management port provides a control interface to control the power module. The non-management ports each lack the control interface of the management port, and each provide a signal indicating that the power module has a sufficient amount of the stored energy to power a defined operation by external devices coupled to and drawing power from said non-management ports. The management port will typically provide a similar signal to the coupled management device. The signal may be implemented as a high or low voltage level on a serial interface cable pin.

Abstract: A method of restoring an encrypted memory image in a system comprising volatile and non-volatile memory initiates a RESTORE of the image from the non-volatile memory to the volatile memory during a BIOS phase of a boot process for the system. If, during an operating system phase, it is determined that the RESTORE failed due to a password error, a password is written to the non-volatile memory and the BIOS phase of the boot process is reinitiated.

Abstract: A sequential delay mechanism is provided for a memory subsystem of a host system. A first independent SAVE region of NVDIMMs of the memory subsystem is configured to start a memory SAVE immediately upon receiving a SAVE signal from the host system, and other independent SAVE regions of the NVDIMMs are configured to implement the delay mechanism. A memory SAVE to the NVDIMMs is activated immediately in the first independent SAVE region when the SAVE signal is received, and the other independent SAVE regions sequentially delay their activation of the memory SAVE.

Abstract: A memory module is organized into slice sections, each configured to input and output a slice of data for a different section of a data bus. Each slice section includes at least one nonvolatile memory (NVM) and a memory element, such as random access volatile memory, to store the slice of data for the slice section during operations that transfer the slice of data between the section of the data bus for the slice section and the NVM of the slice section. Each slice section also includes a slice controller configured to translate an address for the slice of data for the section of the data bus into a physical address of the NVM of the slice section.

Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.

Abstract: A non-volatile memory module includes a volatile memory circuit; an interface to a reference voltage source external to the module providing an external reference voltage to the volatile memory circuit by which the volatile memory circuit and external devices may communicate reliably at high speeds; an internal reference voltage generator; and a control circuit adapted to cause the volatile memory circuit to be decoupled from using the external reference voltage and coupled to using a reference voltage from the internal reference voltage generator upon the non-volatile memory module ceasing to draw power from an external power source.

Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.

Abstract: A circuit includes a series arrangement of capacitors and a balancing circuit coupled to the series arrangement of capacitors, the balancing circuit having drive circuits each coupled at a node in the series arrangement at which two of the capacitors are coupled in series. The drive circuit includes an output stage having switches arranged to either push or pull current from a drive circuit output depending on the state of the switches.

Abstract: A memory system distributes across multiple pages of a flash memory bits of a DRAM data word, the data word having a number of bits equal to a width of a row of a DRAM memory, and the bits of the data word all from a same row of the DRAM memory.

Abstract: A memory module includes a volatile memory, a non-volatile memory, and a memory controller adapted to present to a host system external to the memory module an address space that includes an address space of the volatile memory and excludes all addresses of the non-volatile memory capacity. The module includes logic to copy the contents of the volatile memory to memory locations of the nonvolatile memory capacity reserved for backup of the volatile memory, using power from a backup power interface, when suitable power from the host system is unavailable, wherein the memory controller reserves for backup of the volatile memory an amount of nonvolatile memory storage capacity that is at least twice a memory storage capacity of the volatile memory.

Abstract: A memory module includes volatile memory and non-volatile memory. The module includes logic to check if a non-volatile memory comprises un-erased areas, and if the non-volatile memory comprises un-erased areas, to elevate a backup capacitor potential above a predetermined operating potential sufficient to power a backup of a volatile memory to the non-volatile memory. The module includes logic to ERASE the un-erased areas and to return the capacitor to the predetermined operating potential after the ERASE is complete.

Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.

Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.

Abstract: A method of managing the charge stored by a series arrangement of capacitor stages, each stage including a single capacitor or a plurality of capacitors in parallel, involves supplying each capacitor stage with charge current via a common charging terminal; separately measuring a stored potential of each capacitor stage in the series arrangement; selectively removing a controlled amount of charge from each of the capacitor stages individually) while the series arrangement is receiving the charge current from the common charging terminal; and maintaining each capacitor stage at a substantially equal stored potential.

Abstract: A circuit includes a series arrangement of capacitors and a balancing circuit coupled to the series arrangement of capacitors, the balancing circuit having drive circuits each coupled at a node in the series arrangement at which two of the capacitors are coupled in series. The drive circuit includes an output stage having switches arranged to either push or pull current from a drive circuit output depending on the state of the switches.

Abstract: A device includes a backup power supply configured to provide power to an external system upon loss of primary system power, the backup power provided by at least one capacitor; logic to create, while the capacitor is available as the backup power supply to the external system, a transient elevation of the capacitor's stored potential above a upper predetermined operating potential of the capacitor; logic to obtain measurements of the capacitor's output voltage during the transient elevation of the capacitor's stored potential; and logic to determine a capacitance of the capacitor from the measurements; the device comprising multiple capacitors in series; logic to discharge each capacitor in series individually from the others; and logic to monitor for overcharging of any of the capacitors in series, and, during charging of the capacitors in series, to operate the discharge logic for any capacitor in the series that is in danger of overcharging.

Abstract: A memory module includes volatile memory and non-volatile memory. The module includes logic to check if a non-volatile memory comprises un-erased areas, and if the non-volatile memory comprises un-erased areas, to elevate a backup capacitor potential above a predetermined operating potential sufficient to power a backup of a volatile memory to the non-volatile memory. The module includes logic to ERASE the un-erased areas and to return the capacitor to the predetermined operating potential after the ERASE is complete.

Abstract: A process of interacting with a memory module to restore data backed up from volatile memory to nonvolatile memory of the memory module involves a host system configuring the volatile memory of the module to interoperate with a host memory controller via a DIMM memory interface to the module; the host configuring a controller of the module to copy data from the nonvolatile memory to a peripheral I/O bus, the configuration of the controller of the module carried out via the peripheral I/O bus; a host I/O controller receiving the data copied to the peripheral I/O bus and communicating the received data to a host memory controller; and the host memory controller copying the received data to the volatile memory via the DIMM memory interface, thus completing a restore of the data from nonvolatile memory to the volatile memory.

Abstract: “A non-volatile memory module includes a volatile memory circuit; an interface to a reference voltage source external to the module providing an external reference voltage to the volatile memory circuit by which the volatile memory circuit and external devices may communicate reliably at high speeds; an internal reference voltage generator; and a control circuit adapted to cause the volatile memory circuit to be decoupled from using the external reference voltage and coupled to using a reference voltage from the internal reference voltage generator upon the non-volatile memory module ceasing to draw power from an external power source.

Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.