Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes evaluating the capacitor stack to determine the efficacy of the sidewall diffusion barrier layer deposition. When evaluating the capacitor stack after etching a masking layer portion of the hard mask, if “ears” are seen on top of the stack, the sidewall diffusion barrier layer is sufficiently thick to provide an adequate sidewall barrier. Evaluation may be performed using a standard or tilt scanning electron microscope, for example.

Abstract: Methods and apparatus are disclosed for selectively coupling sense amps with local IO lines in memory devices, comprising first and second selection systems operable to selectively couple a sense amp terminal with a local IO line. A first selection system is coupled with a local IO line and a sense amp, providing selective coupling thereof a second time period after the sense amp is enabled. A second selection system is coupled with the local IO line and the sense amp, which couples the local IO line with the sense amp a first time period before the sense amp is enabled during a write operation, wherein the first time period may be zero.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.

Abstract: In one embodiment, the present invention recites forming a number of first openings in a first substrate. The present embodiment then recites forming a copper region within each first openings during a damascene process, wherein each copper region has a top surface. The present embodiment then disposes a dielectric layer proximate to the top surface of each of the first copper regions during the damascene process. After depositing a second substrate over the dielectric, a number of second openings in a second substrate are made. Next, a number of second copper regions are formed in the second openings, during the damascene process. The dielectric region is thus disposed between the first copper regions and the second copper regions. In so doing, the dielectric region forms a dielectric barrier between the first copper regions and the second copper regions such that a metal-insulator-metal (MIM) capacitor is formed during a damascene process.

Abstract: In one method embodiment, the present invention recites forming an opening in a substrate during a damascene process. The present embodiment then recites forming a dielectric region having two curvilinear surfaces opposite one another at least partially within the opening during the damascene process. The surfaces are curvilinear with respect to a horizontal cross-section. The present embodiment then recites forming a first copper region having a curvilinear surface proximate one of the surfaces of the dielectric region during the damascene process. The present embodiment then recites forming a second copper region having a curvilinear surface proximate a second surface of the dielectric region during the damascene process. In so doing, the dielectric region forms a dielectric barrier between the first copper region and the second copper region such that the vertical cylindrical MIM capacitor is formed.

Abstract: Integrated circuitry comprises target circuitry and test circuitry. The target circuitry uses a clock signal to transfer a target signal within the integrated circuitry. The test circuitry samples the target signal at a selected time from a plurality of possible times within a clock cycle of the clock signal. The test circuitry samples the target signal in response to a test signal indicating the selected time.