Abstract: An apparatus for powering a low power communication module via a debug interface is provided. By way of example, a wireless communication device includes a low power communication module, an inverting power supply coupled to the low power communication module, a comparator coupled to the inverting power supply, and an input buffer including a capacitor and a diode. The input buffer is coupled to the comparator and is configured to store energy from a transmission signal line of a debug interface of another device. The comparator is configured to enable the inverting power supply to supply power when an amount of energy stored reaches a minimum threshold and switch off the power supply if a power demand is not sustainable or runs the TX line above a predetermined minimum space voltage.

Abstract: An apparatus for powering a low power communication module via a debug interface is provided. By way of example, a wireless communication device includes a low power communication module, an inverting power supply coupled to the low power communication module, a comparator coupled to the inverting power supply, and an input buffer including a capacitor and a diode. The input buffer is coupled to the comparator and is configured to store energy from a transmission signal line of a debug interface of another device. The comparator is configured to enable the inverting power supply to supply power when an amount of energy stored reaches a minimum threshold and switch off the power supply if a power demand is not sustainable or runs the TX line above a predetermined minimum space voltage.

Abstract: An apparatus for saving power in an field programmable gate array (FPGA) in an optical communication device is provided. The apparatus includes at least one ring oscillator having an operating frequency disposed inside the FPGA, a core voltage switching unit configured to supply a core operating voltage to the FPGA, and control logic configured to adaptively output an adjusted new core voltage to the FPGA via the core voltage switching unit. The control logic is configured to output a core voltage control signal to the core voltage switching unit based on the operating frequency of the at least one ring oscillator. The core voltage switching unit is further configured to supply the adjusted new core voltage to the FPGA in accordance with the core voltage control signal.

Abstract: A method and apparatus for controlling delay over a data path in a device for transporting Ethernet packets over an optical transport network. The device is configured to receive an incoming clock signal having a first frequency and an incoming data signal and to output an outgoing clock signal having a second frequency and an outgoing data signal. One or more delays over the data path in the device are measured in a predetermined measurement period. A phase adjustment amount is determined based on the one or more measured delays over the data path in the predetermined measurement period, and based on the determining phase adjustment amount, a phase of the outgoing clock signal is adjusted by a phase locked loop in such a way that the delay over the data path in the device is substantially equal to a fixed delay value.

Abstract: A method and apparatus for controlling delay over a data path in a device for transporting Ethernet packets over an optical transport network. The device is configured to receive an incoming clock signal having a first frequency and an incoming data signal and to output an outgoing clock signal having a second frequency and an outgoing data signal. One or more delays over the data path in the device are measured in a predetermined measurement period. A phase adjustment amount is determined based on the one or more measured delays over the data path in the predetermined measurement period, and based on the determining phase adjustment amount, a phase of the outgoing clock signal is adjusted by a phase locked loop in such a way that the delay over the data path in the device is substantially equal to a fixed delay value.

Abstract: A method and apparatus for controlling delay over a data path in a device for transporting Ethernet packets over an optical transport network. The device is configured to receive an incoming clock signal having a first frequency and an incoming data signal and to output an outgoing clock signal having a second frequency and an outgoing data signal. One or more delays over the data path in the device are measured in a predetermined measurement period. A phase adjustment amount is determined based on the one or more measured delays over the data path in the predetermined measurement period, and based on the determining phase adjustment amount, a phase of the outgoing clock signal is adjusted by a phase locked loop in such a way that the delay over the data path in the device is substantially equal to a fixed delay value.

Abstract: An apparatus for saving power in an field programmable gate array (FPGA) in an optical communication device is provided. The apparatus includes at least one ring oscillator having an operating frequency disposed inside the FPGA, a core voltage switching unit configured to supply a core operating voltage to the FPGA, and control logic configured to adaptively output an adjusted new core voltage to the FPGA via the core voltage switching unit. The control logic is configured to output a core voltage control signal to the core voltage switching unit based on the operating frequency of the at least one ring oscillator. The core voltage switching unit is further configured to supply the adjusted new core voltage to the FPGA in accordance with the core voltage control signal.

Abstract: Disclosed is an electrical transceiver for synchronous Ethernet, including: a first interface connected with a host; a second interface including a physical layer (PHY) transceiver connected with a serial link; and a processor connected with the first interface and the second interface, wherein the processor includes a timing control unit controlling a transmission signal transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface to have the same time delay.

Abstract: Disclosed are apparatuses and methods in data communications for adding new system functions to an existing network element without having to provide software or hardware updates to the existing network element. For example, an apparatus for data communication is configured to include a switching unit, a plurality of interfaces coupled to the switching unit, and a plurality of smart transceivers. The plurality of smart transceivers each comprises a discovery unit and a new system function unit. The discovery unit is configured to discover other smart transceivers coupled to the plurality of interfaces and the new system function unit is configured to add one or more new functionalities to the apparatus without adding software or hardware updates to the apparatus.

Abstract: Disclosed is an electrical transceiver for synchronous Ethernet, including: a first interface connected with a host; a second interface including a physical layer (PHY) transceiver connected with a serial link; and a processor connected with the first interface and the second interface, wherein the processor includes a timing control unit controlling a transmission signal transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface to have the same time delay.

Abstract: Disclosed is an electrical transceiver for synchronous Ethernet, including: a first interface connected with a host; a second interface including a physical layer (PHY) transceiver connected with a serial link; and a processor connected with the first interface and the second interface, wherein the processor includes a timing control unit controlling a transmission signal transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface to have the same time delay.