Abstract: A semiconductor package structure includes a functional die, a heat dissipation component, an adhesive, a molding compound, and a thermally conductive material. A bottom surface of the heat dissipation component is bonded to a top surface of the functional die via the adhesive. The functional die and the heat dissipation component are encapsulated by the molding compound. The thermally conductive material has a physical contact with a top surface of the heat dissipation component, wherein thermal conductivity of the heat dissipation component is higher than thermal conductivity of the modeling compound, and thermal conductivity of the thermally conductive material is higher than the thermal conductivity of the heat dissipation component.

Abstract: A sequence detection device includes a feed-forward filter and a sequence detection circuit. The feed-forward filter processes a received signal to generate an equalized signal. The sequence detection circuit performs sequence detection upon the equalized signal to generate and output a symbol sequence. The sequence detection circuit includes a region estimation circuit and a trellis selection circuit. The region estimation circuit categorizes each of samples included in the equalized signal into one of regions. The trellis selection circuit selects one of trellis schemes for branch metric calculation according to region estimation results of two of the samples output from the region estimation circuit.

Abstract: A sequence detection device includes a feed-forward filter and a sequence detection circuit. The feed-forward filter processes a received signal to generate an equalized signal. The sequence detection circuit performs sequence detection upon the equalized signal to generate and output a symbol sequence. The sequence detection circuit includes a region estimation circuit and a trellis selection circuit. The region estimation circuit categorizes each of samples included in the equalized signal into one of regions. The trellis selection circuit selects one of trellis schemes for branch metric calculation according to region estimation results of two of the samples output from the region estimation circuit.

Abstract: A sequence detection device includes a feed-forward filter, a feedback filter, a combining circuit, a decision circuit, and a sequence detection circuit. The feed-forward filter processes a received signal to generate a first equalized signal. The feedback filter processes a symbol decision signal to generate a second equalized signal. The combining circuit combines the first and second equalized signals to generate a sample signal. The decision circuit performs hard decision upon the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection upon the first equalized signal, and includes a region estimation circuit and a trellis selection circuit. The region estimation circuit is independent of the decision circuit, and categorizes each sample of the sample signal into one region. The trellis selection circuit selects one trellis scheme for branch metric calculation according to region estimation results output from the region estimation circuit.

Abstract: A wireless communication device includes an encoder circuit and a wireless communication circuit. The encoder circuit encodes the same input data to generate and output frames with different encoding quality. The wireless communication circuit receives the frames from the encoder circuit, and transmits at least one frame selected from the frames to another wireless communication device via a wireless link.

Abstract: An Ethernet device includes a link test pulse (LTP) generator circuit, a hybrid circuit, a transmit (TX) circuit, a receive (RX) circuit, and a post-processing circuit. The LTP generator circuit generates an LTP signal that is compliant with an IEEE 802.3 standard. The TX circuit transmits the LTP signal to an Ethernet cable through the hybrid circuit. The RX circuit receives an RX signal from the hybrid circuit during a period in which the LTP signal is transmitted through the hybrid circuit. The post-processing circuit performs a cable diagnosis of the Ethernet cable according to the RX signal.

Abstract: An active noise control (ANC) circuit is used for generating an anti-noise signal, and has a plurality of filters including at least one first filter and at least one second filter. The at least one first filter generates at least one first filter output, wherein each of the at least one first filter has at least one non-static filter and at least one static filter connected in a series fashion. The at least one second filter generates at least one second filter output, wherein each of the at least one second filter has at least one adaptive filter. The anti-noise signal is jointly controlled by the at least one first filter output and the at least one second filter output. The at least one first filter and the at least one second filter are connected in a parallel fashion.

Abstract: A noise reduction (NR) system includes a finite impulse response (FIR) filter and a filter manager circuit. The FIR filter is used to perform NR upon a filter input derived from an input signal. The filter manager circuit is used to determine a configuration of a minimum phase filter according to the input signal, and update the FIR filter by the configuration of the minimum phase filter.

Abstract: A differential successive approximation register (SAR) analog-to-digital converter (ADC) includes a comparator circuit, a sampling circuit, a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, a SAR logic circuit, and a common-mode voltage control circuit. The sampling circuit samples a differential voltage input to generate and output a differential comparator input to the comparator circuit during a sample phase of the differential SAR ADC. The first and second capacitive DACs are coupled to a non-inverting input terminal and an inverting input terminal of the comparator circuit, respectively. The SAR logic circuit controls the first and second capacitive DACs during a SAR phase of the differential SAR ADC. The common-mode voltage control circuit dynamically adjusts an input common-mode voltage of the comparator circuit, wherein the input common-mode voltage of the comparator circuit has different voltage levels during the sample phase and the SAR phase.

Abstract: A sampling system includes a sampler circuit, a first settling error canceller circuit, and a second settling error canceller circuit. During a first phase, each of the sampler circuit and the first settling error canceller circuit perform a sampling operation, and the second settling error canceller circuit performs a holding operation. During a second phase, the sampler circuit and the second settling error canceller circuit perform charge redistribution, and the first settling error canceller circuit performs a holding operation. During a third phase, each of the sampler circuit and the second settling error canceller circuit performs a sampling operation, and the first settling error canceller circuit performs a holding operation. During a fourth phase, the sampler circuit and the first settling error canceller circuit perform charge redistribution, and the second settling error canceller circuit performs a holding operation.

Abstract: A global navigation satellite system (GNSS) receiver includes a multiplexer circuit, a fast Fourier transform (FFT) circuit, a pre-sampler circuit, a code generator circuit, and a hypothesis scheduling machine (HSM). The multiplexer circuit has a first input port, a second input port, and an output port. The FFT circuit is coupled to the output port. The pre-sampler circuit generates and outputs a data sequence output to the first input port of the multiplexer circuit. The code generator circuit generates and outputs a local replica output to the second input port of the multiplexer circuit. The HSM is coupled to the multiplexer circuit, the pre-sampler circuit, and the code generator circuit. Under coordination of the HSM, the FFT circuit is shared between the pre-sampler circuit and the code generator circuit through the multiplexer circuit.

Abstract: A source follower circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a feedback loop circuit. Regarding the first MOS transistor, a gate terminal receives an input signal of the source follower circuit, and a source terminal outputs an output signal of the source follower circuit. Regarding the second MOS transistor, a gate terminal is coupled to a bias voltage, a source terminal is coupled to a first reference voltage, and a drain terminal is coupled to the source terminal of the first MOS transistor. Regarding the third MOS transistor, it is a self-biased diode-connected MOS transistor with its gate terminal coupled to its drain terminal. The drain terminal of the third MOS transistor is coupled to a drain terminal of the first MOS transistor, and a source terminal of the third MOS transistor is coupled to a second reference voltage.

Abstract: The disclosure proposes a method, a non-transitory computer-readable storage medium, and an apparatus for acquiring Global Navigation Satellite System (GNSS) signals. The method is performed by a processor of a baseband integrated circuit (IC) in a GNSS receiver. A search request for starting a search process is received with a maximum current that can be provided to a search engine. The search engine includes a data buffer and a correlation circuitry. The correlation circuitry or the search engine is deactivated when the search process has completed or the search process terminates prematurely.

Abstract: A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.

Abstract: A transconductance-transimpedance (TAS-TIA) amplifier includes a TAS amplifier, a TIA amplifier, and a first common-mode feedback (CMFB) circuit. The TIA amplifier includes a first transistor and a second transistor. The first transistor is coupled between a first TIA output node and a reference voltage. The second transistor is coupled between a second TIA output node and the reference voltage. The first CMFB circuit has a first operational amplifier, a first capacitor, and a first resistor. The first operational amplifier has a first input node for receiving a TIA output common-mode voltage, a second input node, and a first output node coupled to control terminals of the first and second transistors. The first capacitor is coupled between the first output node and the second input node of the first operational amplifier. The first resistor is coupled between the second input node of the first operational amplifier and a reference common-mode voltage.

Abstract: A multi-hypothesis combination circuit includes a coherent combination circuit and a selection circuit. The coherent combination circuit generates a plurality of coherent combination outputs by performing coherent combination according to a plurality of correlation outputs and a plurality of sign sequences, wherein the plurality of correlation outputs correspond to a plurality of channels, respectively, and each of the plurality of coherent combination outputs is derived from the plurality of correlation outputs and one of the plurality of sign sequences. The selection circuit generates and outputs a combination output of the multi-hypothesis combination circuit according to the plurality of coherent combination outputs.

Abstract: A code generator circuit includes a control circuit and a code sequence processing circuit. The control circuit updates an accumulated value by accumulating an increment value per clock cycle, and refers to the accumulated value to generate a control output per clock cycle, wherein the increment value is set based on at least one of a Doppler shift, a block size, and a local replica output sampling rate. The code sequence processing circuit generates a code generator output according to the control output of the control circuit.

Abstract: An inverter circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, a tunable pull-up circuit, a tunable pull-down circuit, and a control circuit. The first MOS transistor has a control terminal configured to receive a first input signal, a first connection terminal, and a second connection terminal. The second MOS transistor has a control terminal configured to receive the first input signal, a first connection terminal, and a second connection terminal coupled to the second control terminal of the first MOS transistor. The tunable pull-up circuit is coupled between the first connection terminal of the first MOS transistor and a first reference voltage. The tunable pull-down circuit is coupled between the first connection terminal of the second MOS transistor and a second reference voltage. The control circuit adaptively adjusts pull-up strength of the tunable pull-up circuit and pull-down strength of the tunable pull-down circuit.

Abstract: A differential successive approximation register (SAR) analog-to-digital converter (ADC) includes a comparator circuit, a sampling circuit, a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, a SAR logic circuit, and a common-mode voltage control circuit. The sampling circuit samples a differential voltage input to generate and output a differential comparator input to the comparator circuit during a sample phase of the differential SAR ADC. The first and second capacitive DACs are coupled to a non-inverting input terminal and an inverting input terminal of the comparator circuit, respectively. The SAR logic circuit controls the first and second capacitive DACs during a SAR phase of the differential SAR ADC. The common-mode voltage control circuit dynamically adjusts an input common-mode voltage of the comparator circuit, wherein the input common-mode voltage of the comparator circuit has different voltage levels during the sample phase and the SAR phase.

Abstract: The disclosure proposes an apparatus and a method for Global Navigation Satellite System (GNSS) Doppler compensation. A complex multiplication is generated based on a first sample and a second sample, where the first sample is a delayed sample. A Doppler frequency is generated based on the complex multiplication. The Doppler frequency is output to a component of a GNSS receiver to remove Doppler effect from a received GNSS signal.