Abstract: An optical network unit (ONU) used in a passive optical network (PON) includes an optical fiber interface, a sniffer module and a frame format converting module. The optical fiber interface is configured to receive an XGPON Transmission Convergence (XGTC) frame. The sniffer module is configured to output a downstream unprocessed XGEM frame and an upstream unprocessed XGEM frame according to the XGTC frame. The frame format converting module is configured to convert the downstream unprocessed XGEM frame and the upstream unprocessed XGEM frame to respective Ethernet (ETH) frames.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for load balancing of a network processing unit (NPU). A central processing unit (CPU) is coupled to the NPU and the NPU has multiple cores. The method, which is performed by the CPU, includes: reassigning a data stream processed by a first core in the NPU, which is under a high load, to a second core in the NPU, which is under a low load, where the low load is lower than the high load. The data stream is distinguished from other data streams by at least its quintuple, and the quintuple is composed of a source Internet Protocol (IP) address, a source port, a destination IP address, a destination port and a protocol type.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for analyzing an algorithm designed for running on a network processing unit (NPU). The method, which is performed by a processing unit, includes: loading and executing an executable program file on a virtual machine, which includes the algorithm that can be executed by the NPU; generating an instruction classification table during an execution of the executable program file, where the instruction classification table stores information about instructions that have been executed on the virtual machine, and which instruction category each instruction is related to; and generating an execution-cost statistics table according to the instruction classification table and an instruction cost table, thereby enabling the algorithm to be optimized according to content of the execution-cost statistics table.

Abstract: A buffer management apparatus includes a plurality of registers and a buffer block management circuit. The buffer block management circuit is used to communicate with software through the plurality of registers, and utilize pure hardware to manage a plurality of buffer blocks configured in a storage medium, for allowing the software to perform data access upon the plurality of buffer blocks.

Abstract: A link aggregation load balancing apparatus includes a flow monitoring circuit and an initial allocation circuit. The flow monitoring circuit is arranged to monitor flows of a plurality of member ports belonging to a link aggregation group, for performing classification upon the plurality of member ports to generate a member port classification result. The initial allocation circuit is arranged to refer to the member port classification result for selecting a target member port from the plurality of member ports to act as a forward port of a data flow.

Abstract: The present invention provides a method of implementing an ARM64-bit floating point emulator on a Linux system, which includes: running an ARM64-bit instruction on the Linux system; applying an instruction classifier to a first feature code of a machine code indicated by the ARM64-bit instruction to determine whether the ARM64-bit instruction is an ARM64-bit floating point instruction; and, if the ARM64-bit instruction is an ARM64-bit floating point instruction, applying the instruction classifier to a second feature code of the machine code indicated by the ARM64-bit instruction to determine the ARM64-bit floating point instruction to be a specific ARM64-bit floating point instruction.

Abstract: An echo and near-end cross-talk (NEXT) cancellation system includes a time-domain processing module and a frequency-domain processing module. The time-domain processing module is configured to receive an unprocessed signal after an analog-to-digital conversion, remove at least one time-domain dominant component of interference from the unprocessed signal, and accordingly cancel a time-domain processed signal. The frequency-domain processing module is connected to the time-domain processing module, and configured to receive the time-domain processed signal, cancel at least one frequency-domain component of the interference from the unprocessed signal, and accordingly generate a processed signal.