Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: A pixel architecture is provided for complementary metal-oxide-semiconductor (CMOS) image sensors for high dynamic range (HDR) capture without introducing multi-exposure motion blur. The pixel architecture combines a low-noise readout in combination with a shuffle-gate circuit which is used for flexible extension of sensor saturation. The shuffle-gate circuit allows for the overflow charge from a photodiode to be selectively skimmed and stored based on a modulated duty cycle that governs signal range extension. Shared elements allow for further pixel size reduction through wafer-to-wafer interconnects and spatial multiplexing.

Abstract: A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: Digital circuits, and other types of circuits, may be implemented using improved charge domain techniques based on modern silicon processing compatible with standard digital flows. An example of technology that can be used for charge domain digital flows are FINs (as used in FinFET) which can be modified to produce charge domain shift registers and charge domain digital logic. Also, novel notch based implementations which overcome limited potential range, speed, complex clocking and density issues of older generations of charge domain technology may be disclsoed. Such implementations can significantly improve performance, density and reduce power consumption of charge domain digital circuits, with the proper implants and process modifications.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: An interface output for a capacitive sensor has a circuit to sample an input signal from the capacitive sensor, convert the sampled input signal to a digital signal and having an adjustable gain.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: An event driven device has a network collecting data. A device is coupled to the network for determining changes in the data collected, wherein the device signals the network to process the data collected when the device determines desired changes in the data collected. In a second embodiment a level shift adjusts the band diagram of a spill and fill circuit to allow processing only if a change in input value occurs. This is extended to teach a means by which the subset of an image or incoming audio data might be used to trigger an event. It could also be used for always on operation at lower power than alternative solutions.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.