Abstract: The present invention provides a method and apparatus whereby a single engine can manage multiple DMA queues and related functions for a mass storage subsystem such as a RAID array. By operating the engine at a suitably high clock rate, the key buses may be time multiplexed such that each bus operates at substantially its optimum frequency to maintain high efficiency of data throughput. To improve performance further, the DMA addressing function is allocated additional phases whenever the remaining buses have not requested access to the RAID engine.