Abstract: A processor core is accessed. The processor core is configured to execute vector instructions and micro-operations. The vector instructions are converted to micro-operations by a micro-operation sequencer. A VSET instruction includes immediate values that specify an architectural state for vector processing. Changes in architectural state due to VSET instructions are saved as a vector state in a decode unit of the processor core. The saved architectural state serves to reduce the number of instructions that need to get flushed in cases of branch misprediction recovery. A conditional branch instruction is dispatched by the processor core. The dispatching includes storing, by the decode unit, the vector state within the decode unit. The conditional branch instruction is mispredicted. The mispredicting causes one or more erroneous instructions to be executed. The one or more erroneous instructions include erroneously changing the vector state within the decode unit.

Abstract: A network is accessed. The network comprises a plurality of tiles. Each tile in the plurality of tiles includes a mesh switching unit. A communication packet is received by a first tile within the plurality of tiles. The communication packet specifies a target tile within the network. The first tile and the target tile are not adjacent within the network. The communication packet includes a first routing. The first routing includes a first intermediate tile within the plurality of tiles. A second routing is determined by the first tile. The second routing is based on a second intermediate tile within the plurality of tiles. The communication packet is sent by the first tile to the first intermediate tile. The sending includes the second routing. The process continues until the communication packet reaches the target tile within the network.

Abstract: An accelerator is accessed. The accelerator includes a systolic array of tiles that include a plurality of rows and a plurality of columns. Each tile in the systolic array of tiles includes one or more multiply-add units. The accelerator includes a row tail associated with each row within the plurality of rows. A first matrix is multiplied by a second matrix in the systolic array. The multiplying is based on a plurality of partial products. A row within the plurality of rows of the systolic array produces one or more partial products within the plurality of partial products. A last tile within the row forwards the one or more partial products to an associated row tail. The one or more partial products that were forwarded are accumulated with one or more previous partial products associated with the row by the associated row tail.

Abstract: Techniques for coherency management based on coherent hierarchical cache line tracking are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores includes a local cache. A hierarchical cache is coupled to the plurality of processor cores. The hierarchical cache is shared among the plurality of processor cores. Coherency between the plurality of processor cores and the hierarchical cache is managed by a compute coherency block (CCB). A cache line directory is provided for the CCB. The cache line directory includes a core list field and a cache line present field. A cache line operation is detected. The cache line operation is detected by the CCB. The cache line operation is represented by an entry in the cache line directory. The cache line operation is performed, based on corresponding values of the core list field and the line present field.

Abstract: A processor core is accessed. The processor core is coupled to a memory hierarchy. The processor core is configured to execute shadow stack operations and micro-operations. A shadow stack operation is decoded. The shadow stack operation is associated with a shadow stack pointer (SSP). The shadow stack operation is associated with an implementation mode. The shadow stack operation is substituted with at least two micro-operations. The substituting is based on the implementation mode. The at least two micro-operations are then executed. The shadow stack operation includes an SSP push operation. A first micro-operation within the at least two micro-operations includes a store micro-operation. A store address of the store micro-operation implicitly comprises the SSP. An illegal instruction exception is triggered when an operand of the SSP push operation is not one or more specified integer registers.

Abstract: Techniques for sharing processor data within a network are disclosed. A system-on-a-chip (SOC) is accessed. The SOC includes a network-on-a-chip (NOC), which comprises an M×N mesh topology. The mesh includes a coherent tile at each mesh point. Each tile includes local snoop vectors (LSVs). A first coherent tile initiates a snoop operation. The tile generates a snoop vector that indicates other tiles to be notified of the snoop operation. The first coherent tile creates directional snoop vectors (DSVs). The creating logically combines the snoop vector with each of the LSVs. A coherent tile adjacent to the first coherent tile is selected. The adjacent tile is located in a cardinal direction from the first tile. A first DSV is chosen based on the cardinal direction. The first tile sends the snoop operation and the chosen first DSV to the selected adjacent tile.

Abstract: Disclosed embodiments provide techniques for improved performance in processing vector instructions. A processor core is accessed. The processor core is coupled to a memory hierarchy, and the processor core includes one or more vector execution units (VUs), and one or more load store units (LSUs). The processor core includes a vector register file (VRF). The VRF includes multiple vector registers, and each vector register includes multiple vector elements. Vector elements that have a source or destination in contiguous memory are identified. Load store units (LSUs) take advantage of the contiguous memory condition by executing a vector load or vector store operation as a single memory access, requiring a reduced number of clock cycles. The single memory access satisfies each memory operation for each vector element within the vector register file.

Abstract: Techniques for cache management based on cache management using memory queues are disclosed. A plurality of processor cores is accessed. The plurality of processor cores comprises a coherency domain. Two or more processor cores within the plurality of processor cores generate read operations for a common memory structure coupled to the plurality of processor cores. Coherency for the coherency domain is managed using a compute coherency block (CCB). The CCB includes a memory queue for controlling transfer of cache lines determined by the CCB. The memory queue includes an evict queue and a miss queue. Snoop requests are generated by the CCB. The snoop requests correspond to entries in the memory queue. Cache lines are transferred between the CCB and a bus interface unit. The transferring is controlled by the memory queue. The bus interface unit controls memory accesses.

Abstract: A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector floating-point instructions and micro-operations. A vector floating-point instruction is decoded. The decoding includes replacing the vector floating-point instruction with one or more vector floating-point micro-operations (VFPMs). A reorder buffer assigns a reorder buffer ID (ROBID) to each of the one or more VFPMs, in which the assigning includes a micro-sequencer ID (MSID). The processor core executes the one or more VFPMs. The executing includes requiring, by a first VFPM within the one or more VFPMs, a first update to an architectural floating-point flag. The architectural floating-point flag is set, based on the first update. The setting occurs after the one or more VFPMs have been committed by the processor core. A temporary floating-point flag is revised. The revising is based on the first update.

Abstract: A system-on-chip (SoC) is accessed. The SoC includes a mesh network and one or more coherency ordering agents (COAs). The COAs coordinate coherency for one or more processors coupled to the mesh network. The COAs are coupled to one or more communication converters (CCs) by the mesh network. A processor sends a request to a target device. The request is based on a first communications protocol and includes a memory address. The request is sent by a COA to a CC. A request queue within the CC stores the request. The request is checked against one or more additional requests. The CC translates the request, resulting in a converted request, based on a second communications protocol. The translating is based on the checking. The CC transmits the converted request to the target device.

Abstract: Disclosed embodiments provide techniques for prefetching. A processor core that executes instructions out of order (OOO) is accessed. The processor core includes a local cache hierarchy, data prefetch logic, and a prefetch table and is coupled to an external memory system. A first load instruction with a first address is detected and causes a miss in the local cache hierarchy. Information pertaining to the first load instruction is saved in an entry of the prefetch table. The information includes the first address, a confidence count, and an out-of-order mask. A second load instruction with a second address is identified. The information is updated based on the detecting. The information is advanced. The second address is the next sequential address after the first address. The advancing is based on the detecting. One or more data prefetch instructions are issued to the second address plus an offset.

Abstract: Disclosed embodiments provide techniques for communication. A system-on-a-chip (SoC) is accessed. The SoC includes a mesh network that includes a plurality of nodes. At least one node within the plurality of nodes includes a quality-of-service (QoS) agent. Network traffic data is collected by a first QoS agent within a first node. The network traffic data is associated with the first node and the traffic occurs during a first timing window. The first QoS agent receives a request by a primary device within the first node to send data to a secondary device in a second node. The first QoS agent analyzes the network traffic data. A first routing agent within the first node selects an intermediate node within the plurality of nodes, based on the analyzing. The primary device sends the data to the intermediate node.

Abstract: A processor core is accessed. The processor core supports atomic memory operations. The atomic memory operations include multi-operand operations. A compare and swap (CAS) instruction is issued in the processor core. The CAS instruction necessitates three source operands. One of the source operands comprises a destination register. The CAS instruction is split into a plurality of micro-operations. A first value is written from a memory location indicated by a first source operand into a temporary register. A memory word location addressed by a second source operand is accessed using a second micro-operation. The first micro-operation and the second micro-operation are interlocked. Contents of the memory word location are compared. A third source operand is stored to the memory word location addressed by the second source operand. The storing is based on a match of the comparing.

Abstract: A processor core is accessed. The processor core supports virtual memory addressing. The processor core includes a memory management unit (MMU) and a load store unit (LSU). A page table walk is performed by the MMU. The page table walk is responsive to a memory operation. The page table walk identifies a page table entry (PTE) for a virtual to physical address translation. The PTE is read. The reading obtains a first value from the PTE and includes determining, by the MMU, to update one or more status bits within the PTE. The PTE is re-read. The re-reading obtains a second value from the PTE. The PTE is updated to include the one or more status bits, based on a match between the first and second value. The updated PTE is stored in a page table. The re-reading, the updating, and the storing are performed atomically.

Abstract: A processor core is accessed. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A vector memory instruction is decoded. The vector memory instruction is associated with a memory addressing mode. The decoding includes replacing the vector memory instruction with one or more vector memory micro-operations (VMMOs). The one or more VMMOs are substituted with one or more vector memory element micro-operations (VMEMOs). The substituting is based on the memory addressing mode. At least one VMEMO within the one or more VMEMOs is forwarded to a memory queue within a plurality of memory queues. A memory operation is issued to a load-store unit within the processor core. The issuing includes selecting, from the plurality of memory queues, the memory operation. The replacing is based on a micro-operation sequencer. One or more destination registers for the vector memory instruction are determined.

Abstract: Disclosed embodiments provide techniques for instruction execution with a processor pipeline for data transfer operations. A processor core is accessed. The processor core executes one or more instructions out of order. The processor core supports integer operations and floating-point operations. An instruction in the processor core is decoded. The instruction is a data transfer operation. The data transfer operation necessitates a floating-point operation and an integer operation. The floating-point operation and the integer operation are dispatched to one or more issue queues. The floating-point operation and the integer operation are interlocked. The interlocking is accomplished using at least one entry in the one or more issue queues. A first operation of the floating-point operation and the integer operation is executed. A second operation of the floating-point operation and the integer operation is executed. The execution of the second operation is based on the interlocking.

Abstract: Disclosed techniques enable vector instruction processing. A processor core is accessed. The processor core is coupled to a memory hierarchy, and is configured to execute vector operations, scalar operations, and micro-operations. A decode unit decodes a vector memory operation. The vector memory operation is associated with a unit stride addressing mode. The decoding includes dividing the vector memory operation into one or more vector memory micro-operations. A dispatch unit sends at least one vector micro-operation within the one or more vector micro-operations to a scalar request queue within a plurality of request queues. The at least one vector micro-operation is issued to a load-store unit within the processor core. The issuing includes selecting, from the plurality of request queues, the at least one vector memory micro-operation.

Abstract: A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A dispatch unit within the processor core receives a vector memory operation. The dispatch unit sends the vector memory operation to a first vector input queue of multiple vector input queues. The sending is based on the memory addressing mode. A micro-operation sequencer splits the vector memory operation into one or more memory micro-operations, which includes forwarding each micro-operation within the one or more micro-operations to a first memory queue within multiple memory queues. A memory operation is then issued to a load-store unit within the processor core. The issuing includes selecting, from the multiple memory queues, the memory operation. The vector memory operation comprises either a vector load operation or a vector store operation.

Abstract: Techniques for providing a return address stack with branch mispredict recovery are disclosed. A processor core is accessed. The processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic. RAS state information, including a write pointer, a read pointer, and a RAS count, is sent to a branch execution unit. One or more call instructions are detected in an instruction stream. The detecting generates a predicted return address for each of the one or more call instructions which are pushed on the RAS. The pushing is directed by the write pointer. One or more return instructions are recognized in the instruction stream. The write pointer and the read pointer for the RAS are updated, based on information from the branch execution unit. The predicted return address for each of the one or more return instructions is popped from the RAS.

Abstract: An accelerator is accessed. The accelerator includes a weight-stationary systolic array of one or more multiply-accumulate units. The accelerator is coupled to a memory hierarchy and a processor core. The processor core sends a work request to the accelerator. The work request is based on execution of a machine learning model and an activation matrix. In response to the work request, the accelerator loads a weight matrix and the activation matrix. The loading uses the memory hierarchy. The accelerator multiplies the weight matrix by the activation matrix. The multiplication results in an answer matrix. The accelerator stores the answer matrix in the memory hierarchy. The processor core obtains the answer matrix that was stored. The machine learning model is trained. The training produces the weight matrix, which is transposed and saved to the memory hierarchy.