Abstract: A computer system includes sixteen data processors each connected to a communication bus. The communication bus comprises a data bus for carrying data, and an address bus for carrying associated labelling information uniquely identifying the data. Each processor includes read and write detectors connected to the address bus for detecting labelling information of data required by, or presently stored in, respectively, the data processor. A bulk memory having similar read and write detectors is connected to the communication bus. An address generator supplies labelling addresses to the address bus. For each address, one processor or the bulk memory supplies the corresponding data to the data bus, and other processors and/or the bulk memory requiring the data read the data from the data bus. Data is transferred between processors and/or the bulk memory in this way. The address bus and the read and write decoders are configured for multi-dimensional addressing.