Abstract: An active cache memory for use with microprocessors is disclosed. The cache is external to the microprocessor and forms a second level cache which is novel in that it is capable of performing transfers from external random access memory independently of the encache misaligned references and to transfer data to the microprocessor in bursts.

Abstract: A plug-in module receives both primary and alternate power via mating connectors on the module and on the backplane. Multilevel connectors are used so that a module being inserted first receives alternate power and ground before primary power and signal connections are made. The initial connect to the alternate power supply directs the transient current to the alternate power supply through an isolating PN junction diode having a forward bias voltage drop of about 0.8 volts. When the module is fully inserted, the module is connected to both the primary and alternate power. Within each module the associated electrical load is now connected directly to the primary power bus. To prevent transient currents produced by the hot insertion of other plug-in modules from affecting the voltage level on the power bus, the primary voltage supply is connected to the primary power bus via a Schottky diode having a forward bias voltage of approximately 0.4 volts.

Abstract: A multi-port packet-based bridge is described in which packet transmissions on particular ports or between ports may be monitored on another, monitoring port. Efficient operation is realized by using a multi-processor environment and data structures that allow a packet received on one port to be transmitted to multiple ports without being "copied" multiple times. By using a Supervisory Access Terminal, it is possible to specify various circumstances under which a packet will be sent to the monitoring port. These circumstances include monitoring of all packets incoming to a selected port (or ports), all packets forwarded to a selected port (or ports), and packets generated internally and sent to a selected port (or ports). In addition, all packets forwarded from one selected port to another selected port may be monitored. Port monitoring is supported by particular data structures that promote efficient dispatching of packets and by a Bridging Cache that retains the results of recent dispatch calculations.

Abstract: An active cache memory for use with microprocessors is disclosed. The cache is external to the microprocessor and forms a second level cache which is novel in that it is capable of performing transfers from external random access memory independently of the microprocessor. The cache also provides the ability to encache misaligned references and to transfer data to the microprocessor in bursts.

Abstract: An arbitration circuit receives access request signals from ports of a multi-port memory, and generates access grant signals. For one of the ports, the corresponding access request signal is a function of: 1) a signal indicative of a non-negative number N1 such that, at a predetermined time (e.g., at the beginning of a current clock period), a circuit accessing the memory through the port is ready for N1 data words to be transferred through the port, and 2) a signal indicative of whether one or more accesses were already granted to the port to transfer data after the predetermined time (e.g., during the current clock period and the next clock period). In some embodiments, data are read through the port to a pipeline; the number N1 is the number of data word locations in the pipeline that are available to store new data words to be read from the memory. In some embodiments, data are written to the memory from the pipeline; the number N1 is the number of data words held in the pipeline.

Abstract: A computer system and method for transferring data from a first memory to a second memory of a computer system are disclosed. The computer system includes a bus for transferring data between a first module and a second module, at least one of the modules including a shared memory having multiple ports. One port of each shared memory communicates with the bus through a pipeline which includes a plurality of registers connected in series. The pipeline allows shifting data in the registers by one register and loading data from the input of the pipeline into a first one of the registers. An access to one of the shared memories through one port is allowed to proceed simultaneously with a portion of a data transfer between the memories which includes a data transfer through another port and pipeline. The pipelines thus allow shared memories to communicate even when the memories are not simultaneously available for communication with each other.

Abstract: A computer system and method for transferring data between first and second modules of the computer system are disclosed. In a data transfer operation, the data and a signal indicating data presence on a bus are provided on the bus at the beginning of a clock period, and the data are accepted from the bus at the end of at least one clock period including the clock period at the beginning of which the data are provided on the bus.