Abstract: A multi-port packet-based bridge is described in which packet transmissions on particular ports or between ports may be monitored on another, monitoring port. Efficient operation is realized by using a multi-processor environment and data structures that allow a packet received on one port to be transmitted to multiple ports without being "copied" multiple times. By using a Supervisory Access Terminal, it is possible to specify various circumstances under which a packet will be sent to the monitoring port. These circumstances include monitoring of all packets incoming to a selected port (or ports), all packets forwarded to a selected port (or ports), and packets generated internally and sent to a selected port (or ports). In addition, all packets forwarded from one selected port to another selected port may be monitored. Port monitoring is supported by particular data structures that promote efficient dispatching of packets and by a Bridging Cache that retains the results of recent dispatch calculations.

Abstract: A computer system is optimized to perform fast block transfers between modules including local memories that communicate over a multi-master global synchronous bus. Write operations are speeded up by a destination module sending a "ready-to-accept-data" signal before each write request. During a given clock period during which a source module delivers a data word to the bus, the destination module asserts this "ready" signal to indicate to the source module that the destination module is ready for the source module to deliver another word during another, subsequent clock period. The source module can deliver one word per clock period, and the destination module can receive one word per clock period. During a block write, only a starting address for a first word transferred is transmitted, with a counter at both source and destination modules counting each word transferred. Part of the address bus is not used for addresses and instead is used for data.

Abstract: A computer system is optimized to perform fast block transfers between modules that communicate over a multi-master global synchronous bus. Write operations are speeded up by a destination module sending a "ready-to-accept-data" signal before each write request. During a given clock period during which a source module delivers a data word to the bus, the destination module asserts this "ready" signal to indicate to the source module that the destination module is ready for the source module to deliver another word during another, subsequent clock period. The source module can deliver one word per clock period, and the destination module can receive one word per clock period. During a block write, only the starting address for the first word transferred is transmitted, with a counter at both source and destination modules counting each word transferred. Part of the address bus is not used for addresses and instead is used for data.