Abstract: A system is provided for finding the result of a binary operation performed on an array of values, along with its address, in a storage-efficient manner. The system is based on a binary tree structure having a pipeline of binary operators and corresponding multiplexers and storage elements to store the outputs of the multiplexers in addition to the partial addresses of the outputs represented by the outputs of the binary operators. Each computation stage adds one more bit of address until the address is completely known at the last computation stage. The invention reduces the amount of storage required for keeping track of the addresses that are the result of the binary operation.

Abstract: A method and apparatus for performing a fast search in a search-based decoding algorithm. In one embodiment, the Fano sequential decoding algorithm is used in combination with a fast search-based decoding scheme to reduce the latency inherent in the decoding algorithm. The fast search-based decoding scheme provides a method for estimating metrics ahead of time for edges at distance d at least equal to 2. This allows a decision module such as a Fano state machine to readily make a decision as to which direction and edge to proceed on without further metrics calculation.

Abstract: A method and apparatus for producing a variable rate precoded signal are presented in which a variable rate encoder receives a rate control signal and a data signal and generates a constellation size signal and data symbols. The data symbols and constellation size signal can be used by a precoder to produce a variable rate precoded signal. The precoder can be a Tomlinson/Harashima-Miyakawa precoder which uses the constellation size signal as part of the quantization process. The system can also be used to generate a variable rate modulation encoded signal. The invention provides the ability to create a variable rate signal which can be precoded and to which error correcting codes can be readily applied.