Abstract: A hardware copy assist for a data communication switch copies packets in a number required to meet multicasting needs. Packets are read from a switch queue and a home mark is retained for the packet at the head of the queue to facilitate multiple reads and to prevent premature overwrites. Copying decisions may be made incidental to the retrieval of outbound headers from a linked list of table entries to minimize overhead.

Abstract: A hardware copy assist for a data communication switch copies packets in a number required to meet multicasting needs. Packets are read from a switch queue and a home mark is retained for the packet at the head of the queue to facilitate multiple reads and to prevent premature overwrites. Copying decisions may be made incidental to the retrieval of outbound headers from a linked list of table entries to minimize overhead.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.

Abstract: “Per memory” atomic access for a distributed memory multiprocessor architecture is provided by marking bit masks for shared memories to indicate the access privileges of processors to the memories. A processor has access privileges to a shared memory if the bit mask retained for the memory is marked at a bit position reserved for the processor and does not have access privileges if the bit mask is not so marked. A bit mask is permitted to have only one mark at a given time to guarantee that access to each shared memory is atomic.

Abstract: A protocol translation hardware assist for resolving protocol incompatibilities in a multi-protocol switching environment. Discrete information units are transferred seamlessly from inputs to disparate protocol outputs by writing inbound discrete information units into selected address spaces in allocated buffers in a transfer queue in a manner which accounts for protocol format differences while allowing for straightforward dequeueing. The hardware assist fragments inbound discrete information units into multiple outbound units and creates offsets indicated by destination protocol requirements. A bypass check may be implemented to avoid subjecting to the fragmentation inquiry discrete information units for which it can be inferred a priori that fragmentation is not required.

Abstract: A user authentication service for a communication network authenticates local users before granting them access to personalized sets of network resources. Authentication agents on intelligent edge devices present users of associated end systems with log-in challenges. Information supplied by the users is forwarded to an authentication server for verification. If successfully verified, the authentication server returns to the agents authorized connectivity information and time restrictions for the particular authenticated users. The agents use the information to establish rules for filtering and forwarding network traffic originating from or destined for particular authenticated users during authorized time periods. An enhanced authentication server may be engaged if additional security is desired. The authorized connectivity information preferably includes identifiers of one or more virtual local area networks active in the network.

Abstract: A dedicated bandwidth switch backplane has efficient receive processing capable of handling highly parallel traffic. Packets must pass a filtering check and a watermark check before the receive port is allowed to release them to a queue. Highly efficient algorithms are applied to conduct the checks on the packets in a way which expedites receive processing and avoids contention. A hybrid priority/port-based arbitration algorithm is used to sequence filtering checks on pending packets. A watermark comparison algorithm performs preliminary calculations on the current packet using “projected” output queue write addresses for each possible outcome of the queueing decision on the preceding packet and using the actual outcome to select from among preliminary calculations to efficiently address the outcome-dependence of the current packet's watermark check on the queueing decision made on the preceding packet.

Abstract: Shadow arrays are configured in a distributed memory multiprocessor architecture to localize memory referencing. As each additional processor becomes active a variable array having dimensions 1×N, including N single instance variables which must be monitored on a “per processor” basis, is configured in a memory local to the additional processor and made locally referenceable. A patchwork of shadow arrays is thereby established in which each additional processor may reference local memory to access its own value set for the N single instance variables. The single instance formatting of the arrays also advantageously facilitates migration from an single processor operating system to a multiprocessor operating system without substantial recoding.

Abstract: A full duplex repeater for collision-free transmission of data packets between node of a local area network. The repeater includes a multiple of ports, a signal path for communicating data between the ports, and an arbitration mechanism. Each of the ports has an input and output buffer. The mechanism routes data through the repeater by activating each of the ports one port at a time, such as with a round robin algorithm, to transmit stored data from the input buffer of an activated port through the signal path to the other ports. The repeater has a congestion control mechanism that includes level indicators and preset high and low threshold levels for the input buffers and a flow control device. The flow control device monitors the level indicators to determine if the amount of data in a buffer exceeds the high threshold level.

Abstract: A method and apparatus for switching/bridging frames between a heterogeneous media is disclosed. Bridges and/or switches normally bit-swap a MAC header of a frame when switching the frame between heterogeneous media. However, this practice introduces errors in address formats in certain situations. Such problems are resolved by investigating whether a frame to be switched includes local address components, and if so, these address components in the frame are manipulated to ensure that the address formats are proper for a media onto which the frame is being switched.

Abstract: An equalization device has a digital equalizer for joint tuning of a data-carrying signal distorted by analog transmission. The digital equalizer includes a closed-loop automatic gain control (AGC) circuit for applying a compensatory frequency-independent gain to the distorted signal followed by a frequency filter for applying a compensatory frequency-dependent gain to the signal. Joint tuning produces an output signal which more closely resembles the originally transmitted signal, facilitating recovery of implicit clock and more reliable data recovery. The digital equalizer may be advantageously stage-implemented as a preliminary digital equalizer which is preceded by an analog equalizer and followed by a final digital equalizer.