Abstract: An photodetector circuit comprising an avalanche photodiode having a signal input for receiving an input optical signal to be converted to an electrical signal. The photodetector circuit further includes biasing circuitry, coupled to the avalanche photodiode, for applying a bias voltage to the avalanche diode. The bias circuitry includes: (1) a dc bias circuit for providing a dc component to the bias voltage for maintaining the avalanche diode in a stable avalanche gain condition when receiving the input optical signal; and (2) a modulating circuit for providing a high frequency modulating component to the bias voltage for modulating the bias voltage in a manner that enhances the operational characteristics of the avalanche photodiode. In particular, the modulating component to the bias voltage decrease the noise of the signal output of the avalanche photodiode for a given average gain, and increases the bandwidth of the signal output of the avalanche photodiode for a given average gain.

Abstract: A reset pulse generating circuit is disclosed for generating reset pulses that are used for placing digital systems such as microprocessors into a known state upon power-up and when power fluctuations occur. The reset pulse generating circuit includes a memory circuitry and a counter circuitry, and is designed to work in conjunction with a threshold detector circuitry that monitors the level of the power supply voltage and provides a binary output indicating whether the power supply voltage is above or below a threshold value. The memory circuitry includes four series-connected D-type flip flops, the first two of which are resetable in response to fluctuations in the supply voltage and asynchronous to the system clock. The asynchronous reset inputs of the latter flip flops are for coupling to the output of the threshold detector circuitry. The output of the memory circuitry is used to control the counter circuitry. In turn, the counter circuitry provides the reset pulse.

Abstract: A SONET network element receives incoming SONET signals with a receive line interface (2) which stores the incoming data in an elastic store at the recovered line rate while a local interface reads the stored data at the local network element rate, which may vary slightly from the recovered line rate, and which adjusts the received pointers according to the difference between the line and local rates or phase, allowing the payload data to "float" with respect to the boundaries of frames containing both payload data and overhead with pointers; an elastic store monitor performs the comparison between the receive payload rate and the local clock by comparing write addresses at the recovered line rate and read addresses at the local network element rate by a subtraction process which causes pointer adjustments to be made in response to the subtracted difference exceeding selected memory limits. A process for carrying out VT/TU and/or STS/STM pointer interpretation and generation is shown.

Abstract: A SONET formatter circuit (10) receives a parallel STS-1** TX signal (19) from a highspeed interface module. The STS-1** TX signal (19), which contains a floating VT group payload, is demultiplexed into seven parallel VT groups (33). These seven parallel VT groups (33) are converted to serial by a parallel to serial converter (34) and transmitted serially to lowspeed interface modules as DEMUX direction VT group data signals (42, 43). The SONET formatter circuit (10) also receives serial MUX direction VT group data signals (68, 69) from lowspeed interface modules. These serial VT group data signals (68, 69) are converted to seven parallel VT groups (89) by a serial to parallel converter (64). These seven parallel VT groups (89) are multiplexed with overhead data (84) into a parallel STS-1** RX signal (50) which is transmitted to a highspeed interface module. To maintain continuous VT group frame transmissions, a VT group clock generation circuit (72) is required.

Abstract: A dispersion tolerant OC-192 optical transceiver includes the circuitry for implementing the method of reducing optical signal dispersion in a high data rate data stream that travels on an optical fiber communications system. The circuitry includes circuitry for partitioning the high data rate data stream into a plurality of lower data rate data streams. The transceiver transmits the plurality of lower data rate data streams along an associated one of a plurality of separate wavelength channels. A wavelength division multiplexing circuit multiplexes each of the lower data rate data streams on the plurality of separate wavelength channels into a single optical fiber assembly to form a multiplexed signal. The wavelength division multiplexing circuit further transmits the multiplexed lower data rate signal along the single optical fiber assembly.

Abstract: Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.

Abstract: Read and write addresses on the local and line sides of a SONET elastic store are compared at least twice in order to determine any ambiguity in the comparison and, if so determined, foregoing any pointer adjustments that would otherwise have been made.

Abstract: A circuit for recovering a clock signal from incoming data and for retiming the incoming data comprises circuitry for generating a plurality of phased clock signals responsive to a selected frequency and clock recovery circuitry for generating a recovered clock from the plurality of phased clocks and the incoming data. The recovered clock is used to retime the data, which may be either RZ or NRZ data. To recover clock from the incoming data, the presence of a logic "1" is detected in one or more data streams and the phase of the data relative to the phased clocks is determined. Hold circuitry stores the phase information during the interval between logic "1" bits and aligns the phase information with the leading phased clock. Compare circuitry and counter circuitry detect changes in phase information to insure that a change is not merely the result of a metastable anomaly.

Abstract: A method of increasing the attachment bond strength between a first and second object comprising respective first and second materials is disclosed. Each of the first and second materials has a respective first coefficient of thermal expansion at an assembly temperature, and a second coefficient of thermal expansion at an operational temperature. The method has various steps (FIG. 4). An attachment surface of the first material is configured to be nonplanar (FIGS. 3a, 36, 37). The second material is brought to a contact point with the attachment surface of the first material (FIGS. 3b, 46). The first and second materials are heated at the contact point to the assembly temperature whereby at least one of the materials is caused to flow in response to the heat.

Abstract: In an optical fiber telecommunications network for providing both narrowband telephony signals and broadband video services over a single optical fiber using a single optical carrier, an optical distribution shelf includes a plurality of optical distribution units and interface units for interfacing with a controlling microprocessor. The optical distribution units receive baseband TDM telephony signals in serial format and the broadband video signals and function to frequency division multiplex the broadband video signals with the baseband telephony signals. The multiplexed signal is used to frequency modulate an optical carrier for transmission on a single optical fiber.

Abstract: A method and apparatus for identifying at least a portion of a framing pattern in a data stream comprising a plurality of sequential bits. In the method embodiment, the method includes the step of identifying a set of successive candidate bits wherein the identified candidate bits are spaced apart from one another. The successive candidate bits include a first candidate bit, a last candidate bit, and a predetermined number of intermediary bits between the first candidate bit and the last candidate bit. Each of the intermediary bits has a numeric relative position between the first candidate bit and the last candidate bit. The method further includes the step of identifying a group of look ahead bits corresponding to each of the intermediary bits. Each of the groups has a number of look ahead bits, and the particular number of such bit for a given group equals the magnitude of the numeric relative position for the intermediary bit corresponding to the group.

Abstract: In a signal transmission network, such as a data network, having a multiple access bus topology (12) in which many nodes reside and communicate over the same bus, and wherein electrically isolated and/or physically different signal transmission media (17,18,19) are encompassed by the bus (12), and wherein a common protocol is used across the entire network; a multidirectional repeater (10) repeats signals from any one of the signal transmission media to one or more of the other signal transmission media, thereby providing a contiguous logical bus across the different signal transmission media. The multidirectional repeater (10) uses logic transitions, e.g.

Abstract: A high-integrity video distribution signal is provided unidirectionally from one network node to another network node according to a standard digital communications format (ATM; SONET; DS3) that defines digital signal communications in a bidirectional manner with equal bandwidth in each direction. The one network node providing the video distribution signal simultaneously monitors the video distribution signal, e.g. by a modified loopback (in conjunction with optical power monitoring) for providing a performance monitoring function indicative only of performance of the one network node that provides the video distribution signal, wherein the another network node receiving the video distribution signal performs its own performance monitoring and communicates its performance in the network in a manner other than in the bidirectional manner defined in the standard, wherein the end result is providing the same level of performance monitoring and fault isolation that presently exists in a bidirectional system.

Abstract: A method and system are provided for detecting and measuring a phase difference, linearly over a range of 360.degree., between the output signals from a primary stratum clock module (100) and a standby stratum clock module (120) in a telecommunications system, calculating the amount of time needed to delay the standby clock signal (.o slashed.2) enough to cancel the phase difference, and controlling a digital delay line (132) to shift the phase of the standby clock signal (.o slashed.2) accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when the system or user switches operations from the primary stratum clock module (100) to the standby stratum clock module (120), phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system.

Abstract: Existing infrastructures such as DS1 or E1 are used at currently accepted rates to carry a third more information by using a hybrid encoding technique wherein a 4B3T encoding is done for the payload bits, while a 1B1T encoding technique is used for framing information. In this way, for example, a DS1 can be used at 1.54 Mbit per second to carry 2.058 Mbits of binary payload, while respecting the 8 kilobits of framing expected by DS1 hardware. Similarly, for example, an E1 infrastructure can be used at the accepted 2.048 Mbit per second rate to carry 2.560 Mbits of binary payload plus 128 kilobits of binary framing/CRC without having to change the accepted E1 framing techniques.

Abstract: A circuit board having at least one operational characteristic. The circuit board includes a surface and a plurality of conductive pads accessible from the surface and for electrically coupling electrical components to one another. Further, the circuit board includes a plurality of attachment pads accessible from the surface. Lastly, the circuit board includes at least one identification component attached to at least one of the plurality of attachment pads, wherein the identification component comprises a marking for identifying said at least one operational characteristic. The identification component may or may not include an electrical characteristic. If an electrical characteristic is included, an in-circuit tester may be used to measure the electrical characteristic of the identification component and, thus, determine the identifier given the measurement. As an alternative, the measurement may be used to ensure the correct type of identification component is installed on the circuit board.

Abstract: A method and system for performing protection switching in a communications system is disclosed. The disclosed system and method include the ability to detect bit error burst conditions, in which data is highly errored over a brief time and responsive to which the protection switching procedure is not desired. The number of bit errors over a series of sample periods are counted, and the number of errors detected in each sample period is compared against a burst error threshold. A carryover value from the prior sample period (e.g., the number of detected errors above average) is preferably added to the detected errors in the current sample period prior to the comparison, so that error bursts are detected regardless of their alignment with the sample periods.

Abstract: Magnetic amplifier post regulator (54) includes magnetic amplifier (42) that has a main magnetic amplifier winding, reset transistor (76), error amplifier (58), and auxiliary magnetic amplifier winding (220). Magnetic amplifier (42) controllably blocks a portion of the input voltage N.sub.s /N.sub.p V.sub.IN from winding (30) of transformer (18) in response to a controlled resetting condition and produces therefrom a magnetic amplifier output voltage (v.sub.2). Auxiliary output circuit (14) uses the magnetic amplifier (42) output voltage (v.sub.2) to produce the desired auxiliary output voltage (V.sub.OS). Reset transistor (76) controls reset current to magnetic amplifier (42) in response to an error signal from error amplifier (58). Error amplifier (58) compares auxiliary output voltage (V.sub.OS) to predetermined reference voltage (66) and generates the error signal from the comparison. Auxiliary magnetic amplifier winding (220) has a predetermined number of turns (N.sub.

Abstract: A system and method for fast frequency locking are provided in which the phase difference between first and second synchronization signals is measured (22). The frequency difference between the two signals is then determined (24). The frequency of the second synchronization signal is then set to that of the first synchronization signal (26). Thereafter, the feedback loop of a phase-locked loop circuit is closed, with an error signal representative of the phase difference between the first and second synchronization signals being offset by an amount equal to an error signal generated when the frequency of the second synchronization signal is set to that of the first synchronization signal.

Abstract: A method of constructing a circuit for communicating electrical signals and assembled at least in part by an automated assembly machine is disclosed. The automated assembly machine is operable to select from a plurality of components. The circuit includes a material having a first and second surface and a length. A strip conductor is positioned along the first surface of the material. A ground structure is disposed along the length of the second surface. Finally, a low impedance device selected from the plurality of components is electrically coupled to the ground structure on opposite sides of the strip conductor, wherein the coupling of the low impedance device to the ground structure forms a circumferential shield around the strip conductor. Various alternative embodiments, as well as fabrication methodology are also disclosed.