Abstract: A data ciphering device that has special application in implementing the Digital European Cordless Telephone (DECT) standard data ciphering algorithm which requires a lengthy procedure of key loading and logic operations during the stages of pre-ciphering and ciphering which require clocks operating at different frequencies. The device performs parallel mode loading of the shift registers, with a ciphering keyword. It also calculates, in a first cycle, during the pre-ciphering, the values of the bits of each shift register that determine the value of the next shift in order to, in a second cycle, effect parallel mode shifting in these registers with a value equal to the sum of the two previous shift values. During the ciphering process, the shifting is done in the registers, in parallel mode and in a single data clock cycle, with a value equivalent to the serial value obtained by the algorithm.

Abstract: The sensor device uses the flux-gate principle and detects and cancels a second harmonic frequency (2f.sub.o) output by a sensor coil (23). The sensor device includes a master oscillator (1) that provides a stable output that is supplied to a generator (2) which generate two signals which respectively have a basic operating frequency (f.sub.o) and a double basic operating frequency (2f.sub.o or 2fc). The basic operating frequency (f.sub.o) is amplified in a power booster (3) and is connected to drive coil (22) mounted on a core (39) in the sensor head (4) to saturate the core (39). The output signal from the sensor coil (23) of sensor head (4) is filtered in a first bandpass filter (5) to obtain the second harmonic of the sensor coil, the output signal of the first bandpass filter (5) is detected in a phase detector (6) that is also connected to receive the double (2fc) frequency. The phase detector output is connected to a second low filter (7).

Abstract: Based on a phase lock loop structure, having a reference signal generator (1), a first phase detector (2), a low pass filter (3), a VCO (4) and a frequency divider (5), in order to achieve a faster channel switching an maintain the design of the filters to be as simple as possible, a second phase detector (6) is provided that receives the reference signal (9) and a second output signal (11) coming from the frequency divider (5) and shifted 90.degree. with respect to its other output signal (10), and that generates a second phase error signal (13), in quadrature with the first phase error signal (12), that is filtered by a second low pass filter (7) thereby generating a second filtered phase error signal (15). The two filtered phase error signals (14,15) are provided to a quadratic correlator (8) whose output is provided to the VCO (4). Its amplitude is proportional to the difference of frequencies between the reference signal (9) and any of the output signals (10,11) from the frequency divider (5).

Abstract: A manufacturing process for use in manufacturing magnetic field sensor head cores, comprises: providing a core formed of an amorphous ferromagnetic material on which is placed an insulating layer; mounting, a first winding that functions as a drive coil for the core over said insulating layer; providing second (37) and third (38) coils on said core (31) that respectively function as a sensor and a compensating coil for the sensor head; both the second and third coils being wound in form of a hollow cylinder 36 inside of which is positioned an assembly formed by the core 31 and the drive coil 32; supplying a first electric current to the core 31 of the sensor head, said core heating up as said first current flows through said drive winding, supplying a second and alternating electric current to that the one 38 of compensating and sensor coils 37 and 38 that surrounds the core 31 and functions as the compensating winding 38; monitoring a signal induced in the other coil 37 that functions as the sensor winding a

Abstract: Of the type formed by a pseudorandom code generator and a block that performs the synchronizing and the scrambling in parallel which, in addition to the initialization signal, receives as inputs the set of parallel input data and the codes generated by the code generator, and produces the scrambled parallel data at the outputs; the modulo-2 adders used in the feedback loops of the pseudorandom code generator have only two inputs, and the outputs of the code generator in the parallel working time slots tp and tp+1 are related through the expression:C.sub.tp+1 =T.sup.n (nxn).C.sub.tpsimplifying the result accordingly.

Abstract: A communications system for simultaneously conveying voice and data messages is provided in accordance with the teachings of the present invention. In the communications system disclosed a ring transmission medium for the serial transmission of message information is provided. A plurality of taps are disposed along the ring transmission medium and each of the plurality of taps acts to receive connections from a communications module having at least an input and an output and acts to connect the communications module to the ring. Each of the plurality of taps is configured to have its inputs and outputs connected to the ring and act when no communication module is connected thereto to convey message information on the ring directly between the input and outputs of the tap. When a communications module is connected to that tap, message information is applied from the ring to the input of the communications module and from the output of the communications module to the ring transmission medium.