Abstract: A switch controller for a dynamic switch responds to command from a using system to provide control signals to the dynamic switch which causes the switch to establish and breakdown paths between sources and destinations in the using system. The controller includes a plurality of command registers which are temporarily assigned to a command source for receiving command signals, decoding said signals and providing control signals to the switch for establishing or breaking down a switch path. The controller may if desired provide an echo to a selected destination so that proper execution of commands may be ascertained. After the commands are completed the control register is released for reassignment to another command source while an established switch path remains intact. Thus, commands may be received from any source for controlling the switch.

Abstract: An interface for effecting the direct transfer of message segments between an intelligent switch and a microcomputer includes an input buffer, an output buffer and a memory for storing address to be associated with the message segments traversing the buffers.

Abstract: An interface for use with a microcomputer is provided with memory that in one operating mode is used as a first-in first-out buffer, and in a second operating mode allows the direct data transfer across the interface. The interface also includes a means for selecting the operating mode thereof.

Abstract: A cellular array having a plurality of processor cells disposed on a chip and interconnected by an internal bus includes data bus couplers for bidirectionally coupling to one or more external buses. The data bus couplers selectively couple buses having multiple logic levels. The number of logic levels on the coupled buses may differ. The internal bus may comprise a plurality of parallel data lines each having two-level logic such as binary data, whereas the external buses may have four-level logic represented by four voltage levels. Each data bus coupler has two-bit A/D and D/A converters parallelly connected to selectively convert two bits of two-level logic data to multiple level data and vice versa. The data bus coupler also has a logic level selector circuit using bidirectional gates for selective operation between buses having similar or dissimilar logic levels.

Abstract: A template-matching speech recognition system has a plurality of reference templates each having a plurality of addressable positions, each position storing a value corresponding to the probability of the occurrence of a particular binary value in a corresponding position in an utterance template for speech represented by the referenced template. A system bias template having a corresponding plurality of positions for storing values therein that are representative of the probability of the particular binary value occurring in a corresponding position of any utterance template. A match between an utterance template and a reference template is determined when the sum of the stored probabilities from the reference template positions, corresponding to the positions in the utterance template containing the particular binary value, exceed a predetermined threshold.

Abstract: In a cellular array processor at least two of the plurality of processors in a row cooperate together as an address generator so that large amounts of memory external to the array chip may be addressed and in addition so that an address . may be generated onboard for use by the DRAM memory associated with each processor. Based on this structure, a memory with an internal organization that is 256-bits wide may be connected to 16 16-bit processors which would require 256 bits of data. In so doing, a vast number of pins are saved, that is 256 bits of data out of the memory and 256 bits of data into the processing cells by combining the processing cells and memory on the same chip. It is significant that exactly one design of a processing cell may provide both a data processing element and an address processing element. In this way, these cells are interchangeable to maximize the yield and reliability of the device.

Abstract: A communication system for use with a single pair of externally provided telephone wires and a single pair of in-house wires for the provision of full intercom services and/or PABX type features to a plurality of subsets includes a line interface module connected between the single pair of externally supplied wires and a single pair of in-house wires. In addition, each subset is provided with a station adapter module between it and the single pair of in-house wires.

Abstract: A single board multiple option card for expanding the versatility of a host computer includes an onboard microprocessor, a digital signal processor and a switched memory device. The switched memory is accessible by the onboard microprocessor and the digital signal processor under the control of the onboard microprocessor. The card further includes an analog signal interface having a plurality of switches, the positions of which are controlled by the onboard microprocessor. As a result, multiple options are provided by varying the positions of the switches. Typically, such options may include: "Invisible Keyboard"; "Voice Command Over Telephone Lines"; "Voice Store and Forward Over the Telephone"; "Voice Record and Playback"; and "Hands-free Telephone".

Abstract: An optical fiber which has just been drawn from an optical preform is provided with two external hermetic coatings. The primary coating is a metallic or dielectric coating provided by, for example, using a heterogeneous nucleation thermochemical deposition (HNTD) technique. This technique involves passing the fiber through a reaction zone which contains a gaseous medium that includes a reactant which decomposes, or a mixture of reactants which chemically react, at a predetermined temperature, to form the material of the coating. Such predetermined temperature is available from the heat of the fiber forming process which is retained at the fiber surface by means of a shielding element so that additional heating means is not required. The second coating may be deposited, by for example, using an HNTD or a chemical vapor deposition process. The resulting fiber may then be provided with an additional polymer coating layer.

Abstract: A high voltage mass impregnated power cable to be used on land and in shallow waters by including in the cable construction a pressure body having a number of pressure tapes applied in several layers on a bedding between the metal sheath and the tapes. The pressure tapes have good elastic properties and may consist of high quality metal or a strong synthetic material and are applied with a short lay length. The pressure body maintains under all load conditions including no-load, an internal pressure on the cable insulation above atmospheric pressure and high enough to prevent creation of voids in the insulation.

Abstract: A telephone line access apparatus includes a first stage for providing high voltage protection and a second stage filter in series with the first stage. The first and second stages are incorporated within a housing that is adapted to plug into an existing main distribution frame of a telephone central office.

Abstract: A processor apparatus which is capable of performing floating point arithmetic. The processor apparatus includes a plurality of individual processing cells which are interconnected from left to right in a chain so that any of the processor cells can operate to receive a bit of any slice in a digital word. Each cell includes a memory which essentially is coupled via a multiplexer to an arithmetic logic unit, a controllable multiplier quotient store, a controllable loop path, and controllable status path device. Each of these devices are under control of a control mechanism which is included in the cell, and therefore each path can be connected to any other path via various multiplexers utilized in the circuitry. Essentially, each cell includes a multiport RAM, programmable logic arrays which implement the control logic plus path logic which provides the communication between neighboring cells.

Abstract: A method for fabricating a liquid crystal optical cross point switching matrix includes the steps of forming a plurality of pedestals, each pedestal defining one half of a liquid crystal optical switching device that operates independent of critical angle alignment of the optical beams associated therewith.