Abstract: Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of each E1 signal are mapped into the space of one DS1 signal in the logical space. The remaining eight DS0 signals of every three E1 signal are then interleavingly mapped into the space of one DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals are mapped into the logical space in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.

Abstract: Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of the first E1 signal are mapped into the space of a first DS1 signal in the logical space. The 8 DS0 signals of the first E1 signal are then mapped into the space of a second DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals may be mapped into the logical space of two DS1 signals in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.

Abstract: The invention comprises a time slot interchanger and method for multiplexing ISDN D-channel signals into multiplexed signals in a digital communications terminal. One method comprises receiving a frame of communication signals wherein some of the communication signals represent ISDN D-channel signals wherein each ISDN D-channel signal is represented by a first number of data bits and a second number of other bits. A copy of the frame of communication signals is stored in each of a first, second, third and fourth memory during a first frame period. At least some of the stored communication signals are retrieved from the first, second, third, and fourth memories during a second frame period. Multiplexed signals are then assembled wherein at least one multiplexed signal comprises a multiplexed combination of the data bits of ISDN D-channel signals retrieved from at least two of the first, second, third, and fourth memories.