Abstract: An integrated circuit product includes a first chip, a second chip, a third chip, a fourth chip, a fifth chip, a sixth chip, a seventh chip, and an eighth chip. The areas and constituent components of the first chip, the second chip, the third chip, and the fourth chip are substantially the same. The areas and constituent components of the fifth chip, the sixth chip, the seventh chip, and the eighth chip are substantially the same. The first chip, the second chip, the third chip, and the fourth chip are respectively arranged on the four sides of the integrated circuit product. The fifth chip, the sixth chip, the seventh chip, and the eighth chip are arranged in a central area of the integrated circuit product.

Abstract: An integrated circuit product includes a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent to each other. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent to each other.

Abstract: An integrated circuit product includes a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent to each other. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent to each other.

Abstract: An integrated circuit product includes a first chip, a second chip, a third chip, a fourth chip, a fifth chip, a sixth chip, a seventh chip, and an eighth chip. The areas and constituent components of the first chip, the second chip, the third chip, and the fourth chip are substantially the same. The areas and constituent components of the fifth chip, the sixth chip, the seventh chip, and the eighth chip are substantially the same. The first chip, the second chip, the third chip, and the fourth chip are respectively arranged on the four sides of the integrated circuit product. The fifth chip, the sixth chip, the seventh chip, and the eighth chip are arranged in a central area of the integrated circuit product.

Abstract: An integrated circuit product includes a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent to each other. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent to each other.

Abstract: A high voltage tolerant I/O circuit of an electronic device is disclosed, including a voltage reducing circuit, a first node, a first transistor, a second transistor, and a control logic. The voltage reducing circuit is coupled with a signal pad and utilized for generating a reduced voltage according to an external voltage. When an internal voltage generated by an internal circuit of the electronic device is greater than the reduced voltage, the first node outputs the internal voltage as a first voltage. When the internal voltage is less than the reduced voltage, the first node outputs the reduced voltage as the first voltage. The first transistor is coupled with the signal pad and the first node. The second transistor is coupled with a second terminal of the first transistor and a fixed-voltage terminal. The control logic operates according to the first voltage to control switching operations of the second transistor.

Abstract: A signal generating circuit for a real time clock device is disclosed, having an oscillating circuit, a voltage detecting circuit, and a control circuit. The oscillating circuit is used for generating oscillating signals. The voltage detecting circuit is used for detecting a voltage level coupled with the signal generating circuit. The control circuit is coupled with the oscillating circuit and the voltage detecting circuit. When the voltage level detected by the voltage detecting circuit locates in a predetermined range, the control circuit configures the oscillating circuit to generate the oscillating signals with a larger current at a first interval and to generate the oscillating signals with a smaller current at a second interval. The control circuit further generates a clock signal according to the oscillating signals at a third interval.

Abstract: An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases.

Abstract: An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases.

Abstract: An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases.

Abstract: A high voltage tolerant I/O circuit of an electronic device is disclosed, including a voltage reducing circuit, a first node, a first transistor, a second transistor, and a control logic. The voltage reducing circuit is coupled with a signal pad and utilized for generating a reduced voltage according to an external voltage. When an internal voltage generated by an internal circuit of the electronic device is greater than the reduced voltage, the first node outputs the internal voltage as a first voltage. When the internal voltage is less than the reduced voltage, the first node outputs the reduced voltage as the first voltage. The first transistor is coupled with the signal pad and the first node. The second transistor is coupled with a second terminal of the first transistor and a fixed-voltage terminal. The control logic operates according to the first voltage to control switching operations of the second transistor.

Abstract: A signal generating circuit for a real time clock device is disclosed, having an oscillating circuit, a voltage detecting circuit, and a control circuit. The oscillating circuit is used for generating oscillating signals. The voltage detecting circuit is used for detecting a voltage level coupled with the signal generating circuit. The control circuit is coupled with the oscillating circuit and the voltage detecting circuit. When the voltage level detected by the voltage detecting circuit locates in a predetermined range, the control circuit configures the oscillating circuit to generate the oscillating signals with a larger current at a first interval and to generate the oscillating signals with a smaller current at a second interval. The control circuit further generates a clock signal according to the oscillating signals at a third interval.

Abstract: An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases.