Abstract: Implementing daisy chained ATA host controllers in a single PCI device. The present invention discloses a PCI card that includes a plurality of dominant chips, each of the dominant chips supporting at least one ATA host controller. The PCI card also includes a Flash memory for holding dominant chip settings, an arbiter to control and determine access between the dominant chips and the PCI local bus, and a plurality of ATA connectors corresponding to the ATA host controllers. Each dominant chip includes a byte of memory reserved as a mask to control access to an additional function that may be provided by the dominant chip.

Abstract: A method and a related apparatus for controlling a transmission interface between a computer system and an external device is disclosed. The external device includes a bridge circuit for controlling the transmission interface of the external device, a driver circuit for controlling the external device according to outputs of the bridge circuit, and a memory connected to the driver circuit for storing transmission interface data. Before the computer system obtains the transmission interface data, the bridge circuit transmits a control command to the driver circuit such that the driver circuit retrieves the transmission interface data stored in the memory, and transmits the transmission interface data to the computer system such that the computer system can properly transmit data to the bridge circuit according to the transmission interface data.

Abstract: A pulse duty cycle automatic correction device has a pulse width detector for detecting the high, low level pulse widths of the input cycle pulse so as to generate high, low level signals; a comparator encoder for comparing the high, low level signals, calculating out a correction delay time, and generating a correction delay signal and an output selection signal; a delay circuit for generating a delay cycle pulse; a compensation circuit for compensating the input cycle pulse so as to generate an input compensation pulse; a logic circuit for generating two cycle pulses according to the delay cycle pulse and the input compensation pulse; and a multiplexer for receiving the two cycle pulses and the input cycle pulse, and generating the output cycle pulse with duty cycle of 50% according to the output selection signal.

Abstract: A method includes generating N reference clocks with period T and phases uniformly distributed in 360 degrees; using each of the N reference clocks to trigger M intermediate signals with period M*T and phases uniformly distributed in 360 degrees; and performing a logic operation between at least two intermediate signals respectively corresponding to two different reference clocks to generate an output clock with period (M/N)*T to achieve non-integer frequency division.

Abstract: Method and related apparatus for realizing frequency-multiplication by generating a high frequency signal according to a plurality of low frequency signals. The method includes: according to a plurality output signals generated by a phase-locked loop (PLL) or a delay-locked loop (DLL), generating a plurality of reference signals with a same frequency and different phases; when a number of the reference signals with signal level high is greater than a number of the reference signals with signal level low, making a signal level of the output signal remains a first level; otherwise, making the signal level of the output signal remains a second level substantially different from the first level. Thus the frequency of the output signals is a multiplication of the frequency of the input signals.

Abstract: A method for motion vector de-interlacing decodes macro blocks in a picture, calculates motion vectors of the each MB, produces de-interlacing flag according to the threshold, realizes a Temporal Extension action and performs a Devour action. The Temporal Extension action checks multiple flag buffers, determines if a de-interlace flag should be set as WEAVE or BOB2 based on whether there exists a predetermined number of BOB flags in those flag buffers The Devour action determines if the de-interlace flag is BOB. If positive, it calculates the amount of BOB data within a predetermined area around the current MB, determines if the result is smaller than the BOB threshold and sets the de-interlace flag as WEAVE. Otherwise, it calculates the amount of the WEAVE data, determines if the result is smaller than the WEAVE threshold and sets the de-interlace flag as BOB2.

Abstract: A method of controlling an optical drive to perform a braking process in a layer jump process. The optical drive has a vertically movable pickup head, a preamplifier, a controller, and a low pass filter. The controller receives a focus error signal produced by the preamplifier to produce a focus control signal, and sends the focus control signal to the low pass filter to produce a layer distance balancing signal, so that the pickup head is controlled by the layer distance balancing signal to perform the layer jump process. The method of the present invention comprises the steps of: performing the braking process in accordance with a braking signal and the layer distance balancing signal when the focus error signal reaches a braking start point; and performing a closed-loop focusing control process when the focus error signal reaches a closed-loop focusing control point.

Abstract: An internal circuit structure of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the semiconductor chip, a plurality of signal circuit macros being positioned inside the bonding pads of the semiconductor chip, and an electro-static discharge clamping circuit ring between the signal circuit macros and the inner row of the bonding pads. The bonding pads are positioned in at least four rows along each side of the semiconductor chip, in which the four rows has an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads. Each of the signal circuit macros is positioned to align to the corresponding bonding pads.

Abstract: An internal circuit structure of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the semiconductor chip, a plurality of signal circuit macros being positioned inside the bonding pads of the semiconductor chip, and an electro-static discharge clamping circuit ring between the signal circuit macros and the inner row of the bonding pads. The bonding pads are positioned in at least four rows along each side of the semiconductor chip, in which the four rows has an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads. Each of the signal circuit macros is positioned to align to the corresponding bonding pads.

Abstract: An integrated capacitor including a semiconductor substrate is disclosed. An outer vertical plate is laid over the semiconductor substrate. The outer vertical plate of a plurality of first conductive slabs connected vertically using multiple first via plugs. The outer vertical plate defines a grid area. An inner vertical plate is laid over the semiconductor substrate in parallel with the outer vertical plate and is encompassed by the grid area defined by the outer vertical plate. The inner vertical plate consists of a plurality of second conductive slabs connected vertically using multiple second via plugs. A horizontal conductive plate is laid under the outer vertical plate and inner vertical plate over the semiconductor substrate for shielding the outer vertical plate from producing a plate-to-substrate parasitic capacitance thereof. The inner vertical plate is electrically connected with the horizontal conductive plate using at least one third via plug.