Abstract: A clock duty cycle calibration and frequency multiplier circuit used in a square wave frequency multiplier has a multiplexing module, which performs a phase-inversion operation on a clock signal according to a control signal; a calibration module which adjusts the duty cycle according to a control signal, and outputs a clock signal with a 50% duty cycle; a delay module, which performs a delay operation on the clock signal according to a control signal; a detection module, which compares the clock signal and outputs a feedback signal; a control module, which outputs a control signal according to the feedback signal; a frequency multiplication module, which performs a frequency multiplication operation on the clock signal. Therefore, high-precision clock signal frequency multiplication is implemented with relatively low circuit complexity and low cost.