Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.

Abstract: A method is provided for prioritizing the entries in a database, where each entry is composed of multiple dimensions. Prioritization is required when there are multiple matches in the database. The number of matches can be the same as the number of entries in the database. To prioritize such a huge number of entries in a minimum number of clock cycles, a distributed prioritizer is implemented by partitioning stored binary data into half nibbles comprising of two bits of data each. Each half nibble is encoded into an expanded format allotting priority value to the stored encoded half nibbles. The stored encoded half nibbles are compared across a word array to determine an exact match.

Abstract: A range check array structure for searching and comparing external data from an external search data key is disclosed. The structure has data storage means with at least one of an upper limit field, and a lower limit field, and one or more bit lines running therethrough for transmitting an input data word for comparison with the stored data word range. The input data word being compared with a respective stored data word to detect a match that is indicated along a match line by the check array structure. The check array structure further includes a range match detection means connected to the match line to determine the match or mismatch of the applied data stream with the stored data in each range check cell.

Abstract: A method and device to emulate impedances includes a pair of impedances connected in series between two circuit nodes, the impedances forming a voltage divider having at its midpoint a reference voltage VX. An OP AMP includes a positive input connected to the VX—node and the negative input connected to the output thereof in a direct feedback loop. The OP AMP output is also connected to a load impedance that is connected either one of the nodes. A transistor may be interposed between the load impedance and the circuit node. The OP AMP may be provided with a negative gain to emulate an inductor. The voltage divider may be variable to emulate a variable impedance.

Abstract: Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the memory bank segments are proximally positioned relative to associated I/Os. In this way, the delay times from each of the memory bank segments to their respective I/Os are substantially equal to each other. In addition, the proximal positioning of the memory banks results in reduced signal delays due to reduced signal paths from each bank segment and respective I/O.

Abstract: Techniques for improved erasing of an EPROM are described. As a method, a a drain potential of a first polarity is applied to the drain node of a selected memory cell having a first polarity concurrently with applying a gate potential of a second polarity to the gate of the selected memory cell having a second polarity. The drain and the gate polarities are then maintained until the charge has been removed from the floating gate structure of the selected memory cell as determined by a verification protocol.

Abstract: Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the virtual memory banks has coupled to it an associated segmented sense amp which responds to an appropriate bank select signal by sensing data stored in a selected memory bank segment. The segmented sense amp uses a segmented bit line to reduce bit sense latency without decreasing bit density or increasing chip size.

Abstract: The power consumed by a voltage translator circuit, such as a TTL-to-CMOS buffer, is substantially reduced by changing the supply voltages provided to the input inverter. By reducing the supply voltage provided to the source of the p-channel transistor of the input inverter, the lowest logic-high TTL voltage applied to the gate turns off the p-channel transistor and turns on the n-channel transistor of the input inverter. By increasing the supply voltage provided to the source of the n-channel transistor of the input inverter, the highest logic-low TTL voltage applied to the gate turns off the n-channel transistor and turns on the p-channel transistor.

Abstract: In one aspect, the present invention provides a method for erasing a semiconductor device that comprises applying a voltage pulse at the source of the semiconductor device and a multiple step voltage pulse of the opposite polarity at the gate of the semiconductor device. The multiple step voltage pulse comprises at least a first voltage pulse and a second voltage pulse at the gate of the semiconductor device. The second voltage pulse is usually greater in magnitude than the first voltage pulse. In another aspect, the present invention provides a method for erasing a semiconductor device that comprises applying a substantially constant positive voltage pulse for a first time interval, t1, at the source of the semiconductor device. A first and then a second negative voltage pulse are also applied at the gate of the semiconductor device for a second and third time interval, t2 and t3, respectively. The second negative voltage pulse is greater in magnitude than the first negative voltage pulse.

Abstract: An SRAM array includes resistive loads. These loads are made from resistance sheets formed over polysilicon rails which have vertically extending sidewalls relative to the substrate. The polysilicon rails form vertical area enhancing structures over which the resistance sheets are formed. The resistance sheets include substantially vertical components and substantially horizontal components. The resistance sheets are patterned to form current limiting devices within memory cells of the SRAM array. The polysilicon rails are deposited onto the substrate. Alternatively, the polysilicon rails are deposited onto a field oxide layer of the substrate. An oxide layer is then formed over the polysilicon rails. A second polysilicon layer is formed over the oxide layer, thereby forming the resistance sheet. The resistance sheet has a greater effective length, including the length of the vertical and horizontal components, than the length within which the resistance sheet is contained.