Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.

Abstract: A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.

Abstract: A graphic data compression device includes a processing unit for processing graphic data and a mixed-type compression unit for compressing the data processed by the processing unit. The mixed-type compression unit includes a lossless compression module and a nearly-lossless compression module. The lossless compression module performs a compression on processed data by a lossless compression algorithm. The nearly-lossless compression module includes an adjustment module and a compression module. The adjustment module performs an adjustment on the processed data to reduce a size of the processed data. The compression module performs, by the lossless compression algorithm, a compression on the data adjusted by the adjustment module. A graphic data compression method of the graphic data compression device is also provided. The graphic data compression device and method of the present invention reduce bandwidth load and memory occupancy, thereby effectively improving the usage of memory capacity.

Abstract: A switch for transmitting data packets between at least one source node and at least one target node is provided. The switch includes a storage unit, a control unit, at least one receiving port and at least one transmitting port. The storage unit includes a plurality of storage blocks and configured to cache the data packets. The control unit is configured to manage the storage blocks. The switch receives and caches the data packets transmitted from the at least one source node via the receiving port and transmits the cached data packets to the at least one target node via the transmitting port. A data accessing method adapted for the switch is also provided.

Abstract: A memory-access completion notification associated with a data unit is received from a thread of a pixel shader. A processing status associated with the data unit is obtained from a window buffer. The processing status is updated to indicate that the data unit has not been processed by any thread. The updated processing status is written into the window buffer.

Abstract: An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is disposed on a first surface of the redistribution structure. A second supporting structure has a second opening and is disposed on a second surface of the redistribution structure opposite to the first surface. A first bonding protruding portions are disposed on the first surface of the redistribution structure and located in the first opening. A second bonding protruding portions are disposed on the second surface of the redistribution structure and located in the second opening. A first encapsulated material is filled between the first opening and the first bonding protruding portions. A second encapsulated material is filled between the second opening and the second bonding protruding portions. An electronic structure array is also provided.

Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.

Abstract: An electronic structure process includes the following steps. A redistribution structure and a carrier plate are provided. A plurality of first bonding protruding portions and a first supporting structure are formed on the redistribution structure. A first encapsulated material is formed and filled between a first opening and the first bonding protruding portions. The carrier plate is removed. A plurality of second bonding protruding portions and a second supporting structure are formed on the redistribution structure. A second encapsulated material is formed and filled between a second opening and the second bonding protruding portions.

Abstract: A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.

Abstract: An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is disposed on a first surface of the redistribution structure. A second supporting structure has a second opening and is disposed on a second surface of the redistribution structure opposite to the first surface. A first bonding protruding portions are disposed on the first surface of the redistribution structure and located in the first opening. A second bonding protruding portions are disposed on the second surface of the redistribution structure and located in the second opening. A first encapsulated material is filled between the first opening and the first bonding protruding portions. A second encapsulated material is filled between the second opening and the second bonding protruding portions. An electronic structure array is also provided.

Abstract: An electronic structure process includes the following steps. A redistribution structure and a carrier plate are provided. A plurality of first bonding protruding portions and a first supporting structure are formed on the redistribution structure. A first encapsulated material is formed and filled between a first opening and the first bonding protruding portions. The carrier plate is removed. A plurality of second bonding protruding portions and a second supporting structure are formed on the redistribution structure. A second encapsulated material is formed and filled between a second opening and the second bonding protruding portions.

Abstract: An electrostatic discharge (ESD) protection circuit includes a first n-type transistor, a discharge acceleration circuit and a discharge time circuit. The first n-type transistor has a first terminal coupled to a supply voltage, a second terminal coupled to a reference voltage, and a gate, wherein the first n-type transistor couples the supply voltage to the reference voltage during an ESD event at an I/O pad. The discharge acceleration circuit is coupled to the gate of the first n-type transistor to the I/O pad during the ESD event and coupled to the gate of the first n-type transistor to the reference voltage when there is no ESD event. The discharge time circuit, coupled to the discharge acceleration circuit and the supply voltage, controls a discharge time of the first n-type transistor of coupling the supply voltage to the reference voltage during the ESD event at the I/O pad.

Abstract: Data storage system and management method thereof are provided. The method, adopted by a data storage device coupled to a host device via a bus, includes: determining the data storage device requires to use a first temporary memory of the host device to access data in a second temporary memory of the data storage device; based on the determination, issuing a Device Bus Master (DBM) request message via the bus to the host to request for a right to control data transfer on the bus; in response to the DBM request message, detecting the bus to determine whether to receive a first DBM acknowledgement message from the host device; and if the first DBM acknowledgement message is received, then accessing the first temporary memory of the host device.

Abstract: A delay-locked-loop (DLL) that has increased precision and a wide range of operation is formed by utilizing a chain of delay blocks to add or subtract a discreet amount of delay, and a voltage-controlled delay line (VCDL) to add or subtract a smaller amount of delay. The delay blocks allow the delayed clock signal to get close to the reference clock signal, while the VCDL allows the delayed clock signal to lock onto the reference clock signal.

Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.

Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.

Abstract: A method is provided for prioritizing the entries in a database, where each entry is composed of multiple dimensions. Prioritization is required when there are multiple matches in the database. The number of matches can be the same as the number of entries in the database. To prioritize such a huge number of entries in a minimum number of clock cycles, a distributed prioritizer is implemented by partitioning stored binary data into half nibbles comprising of two bits of data each. Each half nibble is encoded into an expanded format allotting priority value to the stored encoded half nibbles. The stored encoded half nibbles are compared across a word array to determine an exact match.

Abstract: A range check array structure for searching and comparing external data from an external search data key is disclosed. The structure has data storage means with at least one of an upper limit field, and a lower limit field, and one or more bit lines running therethrough for transmitting an input data word for comparison with the stored data word range. The input data word being compared with a respective stored data word to detect a match that is indicated along a match line by the check array structure. The check array structure further includes a range match detection means connected to the match line to determine the match or mismatch of the applied data stream with the stored data in each range check cell.

Abstract: A low latency method of synchronizing asynchronous data to a core clock in a receiving device. A communication referenced to a transmitting clock that is asynchronous to the core clock is received at a receiving device. The communication includes a synchronization signal which is propagated through a synchronizer in the receiving device to synchronize the signal to the core clock. Upon receipt of the synchronization signal by the synchronizer, a load pointer for loading received data into a buffer synchronous with the transmitting clock is reset. Upon completion of the propagation of the synchronization signal through the synchronizer, an unload pointer for unloaded the data from the buffer synchronous with the core clock is reset. The unload pointer is then offset by an amount that compensates for the delay incurred while the synchronization propagated through the synchronizer.

Abstract: The present invention provides a unique system and method for optimizing packet processing flow in a communications network by minimizing latency associated with packet-forwarding eligibility determinations. The present invention employs a speculative scheme with automatic recovery, including a two-way multithreaded implementation designed to overcome the aforementioned latency issue, including the functionality of enqueuing an incoming packet in both packet memory and a cut through buffer; determining the packet's eligibility for cutting through the buffer; and based on the determination, rolling back the unsuccessful process.