Abstract: A parallel processing computer is disclosed in which a plurality of memory elements (e.g., caches) are accessable by a plurality of processors, and in which a fixed access priority for the processors is varied periodically to reduce differences in processing times between the processors in applications where memory access conflicts occur. The variation in priority is done infrequently enough so as not to disturb the ability of the system to avoid memory access conflicts by falling into a "lockstep" condition, in which the fixed priority combined with a selected interleaving of the memory elements produces a memory access pattern that, for certain memory strides, produces no memory access conflicts.
Type:
Grant
Filed:
January 10, 1991
Date of Patent:
July 21, 1992
Assignee:
Alliant Computer Systems Corporation
Inventors:
Michael L. Ziegler, Robert L. Fredieu, Heather D. Achilles
Abstract: A matrix multiplication method that is particularly well suited for use with a computer having hierarchical memory. The A and B term matrices are broken down into blocks and a sum of a series of outer products is computed in order to generate product matrix blocks. Reads to cache or other faster, high-level storage and writes to main memory are interleaved with the calculations in order to reduce or elimiante processor stalling. Individual blocks may be computed by separate processors without requiring communication of intermediate results.
Abstract: The invention is a method and apparatus primarily for generating pixel representations for the video display of three-dimensional objects projected onto a two-dimensional pixel plane. The scanlines of the pixel plane are associated into N interlaced sets, each set having as members only scanlines having an equivalent vertical pixel location Modulo N. The image memory unit block utilizes both serial and parallel processing. For each color (red, green and blue) and for calculating depths, each image memory unit has a plurality N of Scanline Processors for generating the color or depth data to assign to a given pixel. Each of the Scanline Processors is associated with exactly one of the N sets of scanlines. The image memory units each also include a Master Controller. For certain objects, particularly triangular patches, the Master Controller sets up sequentially each Scanline Processor to render pixels on a specific scanline.
Abstract: A cache memory capable of concurrently accepting and working on completion of more than one cache access from a plurality of processors connected in parallel. Current accesses to the cache are handled by current-access-completion circuitry which determines whether the current access is capable of immediate completion and either completes the access immediately if so capable or transfers the access to pending-access-completion circuitry if not so capable. The latter circuitry works on completion of pending accesses; it determines and stores for each pending access status information prescribing the steps required to complete the access and redetermines that status information as conditions change. In working on completion of current and pending accesses, the addresses of the accesses are compared to those of memory accesses in progress on the system.
Type:
Grant
Filed:
July 22, 1985
Date of Patent:
December 27, 1988
Assignee:
Alliant Computer Systems Corporation
Inventors:
Michael L. Ziegler, Jonathan S. Blau, Robert L. Fredieu
Abstract: A digital computer including a plurality of memory elements, the memory elements being interleaved (i.e., each is assigned memory addresses on the basis of a low order portion of the memory address), a plurality of processors connected in parallel, the processors each having means for initiating an access of data from any of the memory elements simultaneously with accesses of other processors, the memory elements each being capable of accepting an access from just one of the processors during a given cycle, and the memory elements being interleaved so that the memory access patterns generated at a stride of one and a stride of two each meet the conditions that (1) the pattern will tolerate being offset with respect to an identical pattern by a desired offset and any multiple of the offset (wherein tolerating means that no memory access conflicts arise, i.e.