Abstract: Aspects of the present disclosure describe a Schottky structure with two trenches formed in a semiconductor material. The trenches are spaced apart from each other by a mesa. Each trench may have first and second conductive portions lining the first and second sidewalls. The first and second portions of conductive material are electrically isolated from each other in each trench. The Schottky contact may be formed at any location between the outermost conductive portions. The Schottky structure may be formed in the active area or the termination area of a device die. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A circuit includes a vertical conduction gallium nitride-based Schottky diode and a vertical conduction silicon based PN junction diode connected in parallel. The Schottky diode and the PN junction diode are packaged in the same semiconductor package and the PN junction diode does not conduct in response to the Schottky diode being forward biased. In some embodiments, the silicon based PN junction diode has a breakdown voltage lower than a breakdown voltage of the gallium nitride-based Schottky diode. The silicon based PN junction diode enters breakdown in response to the gallium nitride-based Schottky diode being reverse biased to divert a reverse bias avalanche current away from the gallium nitride-based Schottky diode.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: A switching regulator controller for a buck switching regulator incorporates a multi-mode adaptive modulator configured to automatically select between a first operation mode and a second operation mode as a function of the output voltage being generated. In one embodiment, the switching regulator controller compares the output voltage to a comparator reference voltage and is configured to operate in a selected operation mode based on the output voltage. In this manner, a single switching regulator controller can be used in multiple instances of an electronic system to supply circuitry that may have different operational requirements. In one embodiment, the switching regulator controller is configured to operation in a PWM/PFM mode and a PWM mode as a function of the output voltage, which indicates the circuit application to which the switch regulator controller is used to supply.

Abstract: A semiconductor substrate comprises epitaxial region, body region and source region; an array of interdigitated active nitride-capped trench gate stacks (ANCTGS) and self-guided contact enhancement plugs (SGCEP) disposed above the semiconductor substrate and partially embedded into the source region, the body region and the epitaxial region forming the trench-gated MOSFET array.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a termination area surrounding the active cell area and disposed near edges of the semiconductor substrate. The termination area includes a plurality of trenches filled with a conductivity material forming a shield electrode and insulated by a dielectric layer along trench sidewalls and trench bottom surface wherein the trenches extending vertically through a body region of a second conductivity type near a top surface of the semiconductor substrate and further extending through a surface shield region of the first conductivity type. A dopant region of the second conductivity type disposed below the surface shield region extending across and surrounding a trench bottom portion of the trenches.

Abstract: A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first pin and the second pin are located near two adjacent corners of the plastic package body. The bottom surface and two side surfaces of each of the first pin and the second pin are exposed from the plastic package body. Locking mechanisms are constructed to prevent the first pin and the second pin from falling off the power semiconductor package device during a manufacturing cutting process. Portions of the first pin, portions of the second pin, and portions of the plastic package body can be cut off.

Abstract: A unidirectional transient voltage suppressor (TVS) device includes first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter.

Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

Abstract: An integrated circuit includes a guard ring structure including a guard ring with integrated well taps to reduce the silicon area required for the guard ring structure. In some embodiments, the guard ring structure includes an N-type guard ring surrounded by inner and outer P-type guard rings. The N-type guard ring is formed with interleaving deep N-wells and P-wells that are formed on an N-type buried layer and are electrically shorted together. The inner and outer P-type guard rings are formed in P-wells. The interleaving deep N-wells and P-wells of the N-type guard ring may be connected to ground or be left floating. By integrating P-well contacts in the N-type guard ring, P-well contacts, or P-taps, for the P-type guard ring can be eliminated.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.

Abstract: A fault tolerant power supply system includes at least one load switch circuit configured to connect, using a main switch, an input voltage to an output node of the load switch circuit when the load switch circuit is turned on and at least one power channel coupled to the load switch circuit to receive the input voltage. The power channel is configured as a buck converter and includes at least a high-side power switch and a low-side power switch. The fault tolerant power supply system is configured to measure a current flowing through the main switch of the load switch circuit, to determine that the current flowing through the main switch of the load switch circuit has exceeded a current limit threshold, and to disable the main switch of the load switch circuit and the low-side power switch of the power channel in response to the determination that the current flowing in the main switch has exceeded the current limit threshold.

Abstract: A semiconductor device may have an active device region containing a plurality of active devices and a termination structure that surrounds the active device region. The termination structure includes a first conductive region that surrounds the active device region, an insulator region that surrounds the first conductive region, and a second conductive region that surrounds the first conductive region and the insulator region. The active device region and termination structure are formed into a semiconductor material of a first conductivity type. The first conductive region is electrically connected to a gate metal and the second conductive region is connected to a drain metal.

Abstract: A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

Abstract: A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging.

Abstract: In some embodiment, a fuse structure in a semiconductor device uses a metal fuse element connected to a stacked via fuse link connected to a thin film resistive element. The fuse structure can be incorporated in an integrated circuit for EOS protection. In other embodiments, an integrated EOS/ESD protection circuit includes a current limiting resistor integrated with an ESD protection circuit. In some embodiments, the current limiting resistor is formed in an N-well forming the collector of the ESD protection circuit.

Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.

Abstract: A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.

Abstract: A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in one or more source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array.