Abstract: This invention discloses a method for configuring a power MOSFET package by packaging several paralleled and separated MOSFET chips in the assembly. The method further includes a step of connecting the gate pad on each of these MOSFET chips with a low-resistance gate bus. The package resistance and inductance are significantly reduced and switching speed and heat dissipation are substantially improved.
Type:
Application
Filed:
July 30, 2002
Publication date:
October 2, 2003
Applicant:
Alpha & Omega Semiconductor, LTD.
Inventors:
Anup Bhalla, Sik K. Lui, Leeshawn Luo, Yueh-Se Ho
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