Abstract: A video-telephony system comprising a plurality of cameras, each capable of generating a video signal; a plurality of display units which are able to receive video signals from the cameras via a wireless link; a plurality of telephones which are able to communicate with each other; means for identifying a camera convenient for a user of a first one of the telephones; and means for transmitting a video signal generated by the camera to a display unit convenient for a user of a second one of the telephones engaged in a call with the first one of the telephones.

Abstract: A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

Abstract: A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.

Abstract: A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.

Abstract: A processor core comprising an execution unit and a register file, said register file comprising a first plurality of registers accessible to a compiler generated code and a second plurality of registers which can not be accessed by a compiler generated code, whereby the registers of said second plurality of registers are accessible to a low level code.

Abstract: A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.

Abstract: A video-telephony system comprising a plurality of cameras, each capable of generating a video signal; a plurality of display units which are able to receive video signals from the cameras via a wireless link; a plurality of telephones which are able to communicate with each other; means for identifying a camera convenient for a user of a first one of the telephones; and means for transmitting a video signal generated by the camera to a display unit convenient for a user of a second one of the telephones engaged in a call with the first one of the telephones.

Abstract: A data processor comprising: a first processor unit having a first register memory addressable in a first format; a second processor unit having a second register memory addressable in a second format, and being capable of retrieving data from the first processor unit; the second processor unit being capable of executing an instruction including an operand specified by means of a reference to data in the first register memory.

Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grou

Abstract: A processing unit comprising: an execution unit for executing an operation defined by an instruction on a pair of input values; a repeat control unit for causing said operation to be repeatedly executed on successive pairs of values, wherein each repeated execution generates an output value; wherein the instruction includes a repeat indicator, which indicates the number of times the operation is to be executed for that instruction and a condition, the repeat control unit being operable in response to said repeat indicator to determine the number of times the operation is executed by the execution unit, and to cease repeated execution on detection that the output value no longer satisfies said condition whether or not the operation has been executed said number of times.

Abstract: A processor comprising: a scalar processing unit for executing scalar instructions each defining a single value pair; a vector processing unit for executing vector instructions each defining multiple value pairs, the vector processing unit comprising a plurality of value processing units each operable to process one of said multiple value pairs and to generate a respective result; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit.