Patents Assigned to Altatech Semiconductor
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Patent number: 9816942Abstract: A nanotopographic measuring device comprises an input arranged to receive sets of measurement data relating to a semiconductor wafer and memory organized into first and second working tables and a results table. A calculation function is capable of establishing a current surface equation from localized gradient values. The equation is established in such a way as to generally minimize a deviation amount between the gradient values calculated from the current surface equation and the localized gradient values. A reconstruction function calculates localized gradient values from a set of measurement data corresponding to an area of the wafer and completes the working tables with these values. It repeatedly calls the calculation function, each time with a part of the values of the first working table and the second working table corresponding to a portion of the area of the wafer to determine, each time, a current surface equation.Type: GrantFiled: October 4, 2012Date of Patent: November 14, 2017Assignee: ALTATECH SEMICONDUCTORInventors: Philippe Gastaldo, Viviane Leguy
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Patent number: 9777374Abstract: A reactor device for chemical vapor deposition comprises a reaction chamber having a purge gas inlet. A gas discharge channel is linked to the reaction chamber via a circumferential opening in the inner wall of the chamber. The reaction chamber is arranged such that a purge gas stream flows from the purge gas inlet to the discharge channel. The inner wall of the reaction chamber comprises means for exchanging heat with the purge gas, for example, fins.Type: GrantFiled: February 21, 2014Date of Patent: October 3, 2017Assignee: ALTATECH SEMICONDUCTORInventors: Patrice Nal, Christophe Borean, Julien Vitiello
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Patent number: 9389189Abstract: The invention relates to a dark-field semiconductor wafer inspection device including, in the following order, a light source for emitting an incident beam to a wafer along a first axis, a concentrator that is symmetrical in relation to a plane passing through the first and second axes and is provided with a mirror that is elliptically cut along a plane perpendicular to an axis perpendicular to the first axis and has a generator parallel to the first axis, parallel first and second slits being set up sideways in first and second portions of the concentrator at the points for concentrating the light that is scattered by the wafer and reflected by the second and first portions of the concentrator, respectively, and a photomultiplier using a slit.Type: GrantFiled: October 9, 2012Date of Patent: July 12, 2016Assignee: Altatech SemiconductorInventors: Philippe Gastaldo, Frederic Pernot
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Patent number: 9007456Abstract: Semiconductor wafer inspection device comprising a wager transport arm provided with at least one wafer support element, a wafer gripper, the gripper having two distant branches designed to take hold of the opposed edges of the wafer, the gripper being mounted so as to rotate on a shaft in order to be able to rotate the wafer between an approximately horizontal position and an approximately vertical position, and at least two inspection systems placed on one side of the wafer and on the other, in an approximately vertical position symmetrically with respect to the plane passing through the wafer.Type: GrantFiled: May 11, 2009Date of Patent: April 14, 2015Assignee: Altatech SemiconductorInventors: Philippe Gastaldo, François Berger, Cleonisse Serrecchia
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Patent number: 8967081Abstract: Device for treating substrates, comprising a changer having controlled pressure and temperature, a substrate support which is provided in the chamber, the chamber comprising a gas inlet for carrying out a vapor phase deposition, and an upper wall of the chamber provided with a plurality of first channels connected to a first inlet and a plurality of second channels connected to a second inlet, the first and second channels opening into the chamber and being regularly distributed in the upper wall, a heating element provided above the upper wall and a gas discharge ring provided between the upper wall and the substrate support, the upper wall begin electrically conductive and insulated relative to the substrate support so as to be able to apply a voltage between the upper wall and the substrate support.Type: GrantFiled: April 22, 2009Date of Patent: March 3, 2015Assignee: Altatech SemiconductorInventors: Christophe Borean, Jean-Luc Delcarri
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Patent number: 8654324Abstract: The invention relates to a device for inspecting the edge of semiconductor wafers, including a chromatic confocal microscope with a lighting pathway and an analysis pathway, the lighting pathway including a polychromatic light source, a slot and an axial chromatism objective lens comprising a lens at least made of a material having an Abbe number lower than 50, and the analysis pathway includes said objective lens, a chromatic filtering slot with a light intensity sensor in that order, the slot of the lighting pathway and the slot of the analysis pathway being provided at substantially the same optical distance from the edge of the wafer to be inspected.Type: GrantFiled: February 23, 2010Date of Patent: February 18, 2014Assignee: Altatech SemiconductorInventor: Philippe Gastaldo
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Publication number: 20130125819Abstract: The reactor includes: a chamber having a lower wall, an upper wall and a sidewall connecting the lower wall to the upper wall; a support plate mounted inside the chamber; at least one first supply line for a first gas, and at least one separate second supply line for a second gas; a gas injection device; and a gas collector. The gas injection device includes at least one injector connected to the first supply line and at least one injector connected to the second supply line, the injectors leading into the chamber through at least one inlet provided in the sidewall; all of the injectors of the first supply line and all of the injectors of the second supply line are connected one above the other; and the collector includes at least one outlet in the sidewall, opposite the inlet relative to the support plate, and substantially at the inlet.Type: ApplicationFiled: July 11, 2011Publication date: May 23, 2013Applicant: ALTATECH SEMICONDUCTORInventors: Christophe Borean, Jean-Luc Delcarri, Herve Monchoix, Thierry Remy, Julien Vitello
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Patent number: 7812942Abstract: A method for detecting surface defects, such as slip line type defects, on a substrate designed to be used in electronics, optoelectronics or analogue, including projection of a pattern of light fringes and dark bands onto the substrate, relative displacement of the substrate relative to the pattern, acquisition of a sequence of at least three images of the pattern reflected by the substrate to a sensor, the images corresponding to displacement of the fringes of the pattern, determination of the gradient of the surface of the substrate using displacements of fringes of the pattern, and determination of the presence of a surface defect on the substrate using variations in the gradient of the surface of the substrate. Another embodiment comprises a device using said method.Type: GrantFiled: March 27, 2008Date of Patent: October 12, 2010Assignees: S.O.I. Tec Silicon on Insulator Technologies, Altatech SemiconductorInventors: Cécile Moulin, Sophie Moritz, Philippe Gastaldo, François Berger, Jean-Luc Delcarri, Patrice Belin, Christophe Maleville
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Publication number: 20090051930Abstract: A method for detecting surface defects, such as slip line type defects, on a substrate designed to be used in electronics, optoelectronics or analogue, including projection of a pattern of light fringes and dark bands onto the substrate, relative displacement of the substrate relative to the pattern, acquisition of a sequence of at least three images of the pattern reflected by the substrate to a sensor, the images corresponding to displacement of the fringes of the pattern, determination of the gradient of the surface of the substrate using displacements of fringes of the pattern, and determination of the presence of a surface defect on the substrate using variations in the gradient of the surface of the substrate. Another embodiment comprises a device using said method.Type: ApplicationFiled: March 27, 2008Publication date: February 26, 2009Applicants: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES, ALTATECH SEMICONDUCTORInventors: Cecile Moulin, Sophie Moritz, Philippe Gastaldo, Francois Berger, Jean-Luc Delcari, Patrice Belin