Abstract: A structure for measuring both interconnect resistance and capacitance. The structure comprises a plurality of metallic interconnects, a first circuit for measuring capacitance charging current at a first interconnect and a second circuit for measuring the voltage drop between two positions at a second interconnect. The first circuit includes two electrically connected pseudo-inverters. Two control signals are fed into the two pseudo-inverters such that their associated capacitances are charged and discharged periodically. The first interconnect capacitance is determined by measuring the difference of charging currents between the two pseudo-inverters. A constant current flows through the second circuit and the interconnect resistance is determined by the voltage drop and the constant current.

Abstract: Techniques for actively configuring a programmable circuit using configuration data stored in an external memory are provided. The programmable circuit attempts to read a device identification code from an external memory device using a read instruction. The programmable circuit then attempts to identify the external memory device by matching the identification code returned from the external memory with a code in a first predefined list. A match indicates that the programmable circuit has hardware that can generate instructions that the memory device can recognize. After the programmable circuit identifies the memory device, the programmable circuit sends instructions to the external memory device according to a predefined protocol understood by the memory device. The programmable circuit can also compare a device identification code for a particular memory device with a second list of identification codes to determine whether a user wants the programmable circuit to support that memory device.

Abstract: Integrated circuits are provided that use on-chip data compression and decompression to minimize consumption of interconnect resources. Parallel-to-serial converter circuitry can use time-division multiplexing techniques to compress data. The compressed data may be conveyed between circuit blocks on the integrated circuit using a reduced number of parallel interconnect conductors. After the compressed data has been conveyed to its destination, a serial-to-parallel converter may use time-division demultiplexing techniques to decompress the data. Interconnect resources may be shared by dedicated circuits. With this arrangement, signals can be selectively steered through the appropriate dedicated circuitry to either maximize performance or to use compression and decompression to minimize interconnect resource consumption.