Abstract: In an illustrative embodiment, holes are formed in an insulating layer where the gates of NMOS and PMOS transistors are to be formed; and a hard mask spacer layer is formed on the exposed surfaces. Next, spacers are formed on the sidewalls of the holes by anisotropically etching the spacer layer to remove the portion of the spacer layer exposed at the bottom of each hole while leaving some of the spacer layer formed on the sidewalls of the holes. A high-k dielectric layer is then formed between the spacers; and a metal layer is formed on the high-k dielectric layer. Bulk metal layer is then formed on the metal layer. Chemical mechanical polishing is performed to remove the bulk gate metal down to the insulating layer, thereby isolating individual NMOS and PMOS gate structures.

Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

Abstract: Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain. A plurality of respective scan enable activation elements controls a respective subplurality of the plurality of control elements for connecting a respective subplurality of the plurality of memory elements into the scan chain. Each scan enable activation element is actuated, to connect its respective subplurality of the plurality of memory elements into the scan chain, by a first enable signal common to more than one of the scan enable activation elements, and a second enable signal for that one of the scan enable activation elements. Such scan chain circuitry may be used for entering configuration data into a programmable integrated circuit device.

Abstract: An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state.

Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Abstract: A program compatibility recognition system for an integrated circuit. A programming device 4, including programming software 8, is used to program an integrated circuit 2 such as a field programmable gate array. The programming device provides a revision code 12 to a detection circuit 10 on the integrated circuit. The detection circuit determines if the revision code indicates that the software is compatible with the integrated circuit and, if so, generates an appropriate control signal to permit the programming device to program the integrated circuit.