Abstract: Systems or methods of the present disclosure may provide a computing system that includes a processor and one or more implemented designs in one or more configurable circuits of a programmable logic fabric. The computing system also includes a memory coupled to the programmable logic fabric. The computing system further includes an accelerator that is located in-line between the one or more configurable circuits and the memory. The accelerator is defined using a low-level programming language. The processor is coupled to the accelerator and is configured to enable modification of the definition of the accelerator by converting a high-level programming language to the low-level programming language to change the way that the accelerator operates.

Abstract: An integrated circuit includes a diode for generating a temperature dependent voltage, a resistor divider for generating divided voltages by dividing the temperature dependent voltage, and a multiplexer circuit for selecting one of the divided voltages as a reference voltage used for setting a supply voltage.

Abstract: A method for implementing an artificial neural network in a computing system that comprises performing a compute operation using an input activation and a weight to generate an output activation, and modifying the output activation using a noise value to increase activation sparsity.

Abstract: Systems or methods of the present disclosure may provide a programmable fabric including programmable logic. The programmable logic may include memory, a network-on-chip (NOC), and at least one micro NOC formed with hardened resources in the programmable fabric. Further, the at least one micro NOC may be communicatively coupled to the NOC and to the programmable logic. Additionally, the at least one micro NOC may selectively route data between the NOC and the programmable logic.

Abstract: The present disclosure is directed generally to semiconductor packages, semiconductor package substrates, and methods for making them, which include packages substrates with embedded passive devices positioned between plated through hole vias configured for an improved power delivery network.

Abstract: An integrated circuit includes a filter circuit and a computation circuit that applies emphasis to a data stream in a frequency domain to reduce distortion to the data stream caused by the filter circuit. The emphasis is determined based on the distortion caused by the filter circuit. A circuit design system includes logic synthesis and optimization tools that relax parameters for a first filter circuit to generate relaxed parameters, use the relaxed parameters to generate a second filter circuit that filters data, generate an emphasis vector based on distortion in the data caused by the second filter circuit, and generate a computation circuit that applies the emphasis vector to the data to reduce the distortion in the data caused by the second filter circuit.

Abstract: A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.

Abstract: An integrated circuit includes a digital signal processing circuit. The digital signal processing circuit includes fixed point multiplier circuits, floating point multiplier circuits, and adder circuits. The digital signal processing circuit is configurable to implement a reduction of floating point multiplication operations based on floating point inputs to the digital signal processing circuit using the fixed point multiplier circuits, the floating point multiplier circuits, and the adder circuits.

Abstract: A processing integrated circuit includes a processing core comprising hard logic circuits and a programmable interface circuit configurable to exchange signals between an external terminal of the processing integrated circuit and the hard logic circuits in the processing core.

Abstract: Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and/or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.

Abstract: This disclosure is directed to methods of disaggregating columnar IO operations from a programmable logic fabric using 3-D packaging technology. More specifically, methods of 3-D programmable fabric arrangements that include one or more IO chiplets stacked in a 3-D orientation on a programmable logic fabric main die that includes one or more D2D drivers to enable communication between the one or more IO chiplets and the programmable logic fabric main die. The IO chiplets may be coupled to the programmable fabric main die through connection to the one or more D2D drivers arranged on the programmable fabric main die.

Abstract: A configurable integrated circuit includes a network-on-chip and a response buffer circuit coupled to the network-on-chip. The response buffer circuit includes a direct memory access circuit and a controller circuit. The direct memory access circuit generates read requests and write requests to access memory circuits. The controller circuit provides the read requests and the write requests to the memory circuits through the network-on-chip. The controller circuit exchanges data with the memory circuits for the read requests and the write requests.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes: instructions; and processor circuitry to execute the instructions to: retrieve a random number and a physical unclonable function (PUF) from a trusted environment; generate a virtual PUF (vPUF) based on a trusted operation including the random number and the PUF; and store the vPUF and the random number in a persistent storage.

Abstract: A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Specifically, a buffer of the extension architecture may be used to load data to and store data from the programmable fabric.

Abstract: An integrated circuit includes a multiplexer circuit coupled to receive a first clock signal and a second clock signal and coupled to provide an output clock signal to a channel. A protection circuit is coupled to receive a feedback signal from the channel. The protection circuit causes the multiplexer circuit to provide oscillations in the second clock signal to the output clock signal in response to the feedback signal indicating that the channel is idle to cause the channel to be in a protection mode that reduces degradation from bias temperature instability. The protection circuit causes the multiplexer circuit to provide oscillations in the first clock signal to the output clock signal in response to the feedback signal indicating that the channel is active.

Abstract: An integrated circuit includes a first input/output lane comprising first external terminals and first driver circuits. The first driver circuits exchange signals with a first external device through the first external terminals as part of a first external interface. The first input/output lane is part of a sub-bank in an input/output bank that implements at least a part of the first external interface. The integrated circuit includes a second input/output lane comprising second external terminals and second driver circuits. The second driver circuits exchange signals with a second external device through the second external terminals as part of a second external interface. The second input/output lane is part of the sub-bank in the input/output bank that implements at least a part of the second external interface.

Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

Abstract: A circuit system includes a processing circuit, an accelerator circuit, and a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit. The buffer circuit functions as a crossbar circuit by allowing each of the accelerator circuit and the processing circuit to access at least one of the packets of data stored in the buffer circuit during access to another one of the packets of data stored in the buffer circuit.

Abstract: A configurable integrated circuit includes first logic circuits, second logic circuits, and a crossbar switch circuit. The crossbar switch circuit includes multiplexer circuits and input busses coupled to the multiplexer circuits. The inputs of each of the multiplexer circuits are coupled to each of the input busses. The configurable integrated circuit is configurable to provide input signals generated by the first logic circuits to the inputs of each of the multiplexer circuits through the input busses. The multiplexer circuits are configurable to provide values of the input signals that are received through the input busses to the second logic circuits.

Abstract: Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.