Abstract: A processing integrated circuit includes a processing core having hard logic circuits and a programmable interface circuit that is configurable to exchange signals between an external terminal of the processing integrated circuit and the hard logic circuits. The processing integrated circuit is one of a microprocessor, a central processing unit, or a graphics processing unit.

Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

Abstract: Techniques to shared system memory across nodes in a system. Circuitry is arranged to provide a mechanism to share a memory region of a memory maintained at a first host CPU at a first node across multiple other host CPUs at multiple other nodes using various links and protocols described in one or more revisions of the Compute Express Link (CXL) specification.

Abstract: The present disclosure is directed to enabling operation of a field programmable gate array (FPGA) while preventing application quiescence during FPGA reconfiguration. In embodiments of the disclosure, proxy agent firmware may enable downstream transactions (e.g., PCIe transactions) to be serviced during reconfiguration of the FPGA. Programmable logic states (e.g., PCIe configuration states or memory-mapped input/output (MMIO) states) are saved in memory and maintained by the proxy agent (via a management controller running the proxy agent). Once the FPGA is reconfigured, the state may be restored to the FPGA's programmable logic, and the FPGA may operate on the current state of the transactions.

Abstract: An integrated circuit includes a device coherency circuit, first and second traffic generator processor circuits, first and second interfaces, and a processor control finite state machine circuit that causes the first traffic generator processor circuit to perform first coherency data validation for first data sets and that causes the second traffic generator processor circuit to perform second coherency data validation for second data sets. The first traffic generator processor circuit transmits first traffic for the first data sets to the device coherency circuit through the first interface. The second traffic generator processor circuit transmits second traffic for the second data sets to the device coherency circuit through the second interface.

Abstract: An integrated circuit includes first and second memory controller circuits and a load balancing multiplexer circuit that redirects a first read operation from the first memory controller circuit to the second memory controller circuit in response to receiving an indication that the second memory controller circuit has available memory bandwidth. A circuit system includes first and second memory devices, first and second memory controller circuits, and a load balancing multiplexer circuit that sends a write operation to the first memory controller circuit to store data in the first memory device and to the second memory controller circuit to store the data in the second memory device, while performing a number of memory traffic shaping operations.

Abstract: An integrated circuit is provided that includes via-configured structured logic circuitry and an embedded arithmetic block that interfaces with the via-configured structured logic circuitry to perform an arithmetic function. The embedded arithmetic block includes at least one monolithic arithmetic circuit that can perform the arithmetic function more efficiently or taking up less die space than a comparable circuit formed from the via-configured structured logic circuitry.

Abstract: A system including a host device and an integrated circuit. The host device includes a host memory, the host memory storing configuration data. The integrated circuit device includes an integrated circuit and a direct memory access circuitry. The direct memory access circuitry pulls the configuration data from the host memory. The direct memory access circuitry also programs the integrated circuit based on the configuration data.

Abstract: A test power-on-reset detector circuit includes a trip-out detector circuit that generates a trip-out signal indicative of a supply voltage increasing above a trip-out level and a trip-in detector circuit that generates a trip-in signal indicative of the supply voltage decreasing below a trip-in level that is less than the trip-out level. The test power-on-reset detector circuit includes a latch circuit that stores values of the trip-out signal and of the trip-in signal to generate a power-on-reset signal during a test of an integrated circuit to control functional power-on-reset signals. A bandgap reference voltage detector circuit includes an amplifier circuit that amplifies a difference between voltages as offset by a first voltage skew to control a current that affects the voltages. A comparator circuit compares the voltages as offset by a second voltage skew to generate a voltage that indicates when a bandgap reference voltage is stable.

Abstract: An integrated circuit includes a multiplexer circuit coupled to receive a first clock signal and a second clock signal. The multiplexer circuit is coupled to provide an output clock signal to a channel in an external device. The channel is coupled to the integrated circuit through a connection external to the integrated circuit. A protection circuit is coupled to receive a feedback signal from the channel through the connection. The protection circuit causes the multiplexer circuit to provide first oscillations in the first clock signal to the channel in the output clock signal in response to the feedback signal indicating that the channel is active. The protection circuit causes the multiplexer circuit to provide second oscillations in the second clock signal to the channel in the output clock signal in response to the feedback signal indicating that the channel has been idle for a period of time.

Abstract: An integrated circuit device that includes programmable logic circuitry that includes a plurality of regions each configured to operate at different voltage levels. The regions may be separated by level shifters that enable communication between the different voltage level regions. The integrated circuitry may also include software that performs voltage aware placement and routing for a user register-transfer level design, and may direct logic to regions according to voltages defined for the regions.

Abstract: Examples described herein relate to a physical layer interface (PHY) that includes circuitry configured to autonomously measure for signal degradation by a baseline measurement of parameters and one or more subsequent measurements of parameters to indicate if link loss is expected.

Abstract: Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

Abstract: A computer system is provided for protecting a circuit design for an application specific integrated circuit. The computer system includes a logic circuit replacement tool for identifying a module of logic circuitry for replacement in at least a portion of the circuit design. The logic circuit replacement tool generates a transformed circuit design for the application specific integrated circuit by replacing the logic circuitry in the module with a configurable circuit that performs a logic function of the logic circuitry when a bitstream stored in storage circuits in the configurable circuit configures the configurable circuit. The transformed circuit design includes the configurable circuit in the module.

Abstract: An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

Abstract: An integrated circuit system includes software-programmable vector processing circuitry having software-programmable vector processors arranged in processing nodes in an array. Each of the processing nodes is communicatively coupled to adjacent ones of the processing nodes in the array through a mesh router. Each of the software-programmable vector processors comprises processing elements. Each of the processing elements is capable of processing first data in a floating point data format. Each of the processing elements is capable of processing integer data. The processing elements comprise hardened circuits that are capable of executing instructions and providing processed data in response to the instructions.

Abstract: Systems or methods of the present disclosure may provide a compilation design method that uses cloud computing resources and/or distributed computing resources to compile initial user designs. The initial user design for the programmable logic device may be partitioned into multiple designs for compilation based on periphery logic and core fabric logic. The compilation design method implements partition-level time budgeting and constraint generation using full device timing analysis. The final placed and routed netlist and bitstream SOF is generated by merging the placed and routed netlist and bitstream SOF of individual partition designs.

Abstract: Systems or methods of the present disclosure may provide a computing system that includes a processor and one or more implemented designs in one or more configurable circuits of a programmable logic fabric. The computing system also includes a memory coupled to the programmable logic fabric. The computing system further includes an accelerator that is located in-line between the one or more configurable circuits and the memory. The accelerator is defined using a low-level programming language. The processor is coupled to the accelerator and is configured to enable modification of the definition of the accelerator by converting a high-level programming language to the low-level programming language to change the way that the accelerator operates.

Abstract: An integrated circuit includes a diode for generating a temperature dependent voltage, a resistor divider for generating divided voltages by dividing the temperature dependent voltage, and a multiplexer circuit for selecting one of the divided voltages as a reference voltage used for setting a supply voltage.