Abstract: An integrated circuit includes an output circuit. The output circuit includes first, second, and third external contacts, a first output buffer circuit coupled to the first external contact, a first resistive circuit coupled between the first external contact and the second external contact, a second output buffer circuit coupled to the third external contact, and a second resistive circuit coupled between the second external contact and the third external contact. The output circuit has a test mode of operation to test for leakage current on the first and the third external contacts in response to receiving a first voltage applied externally to the first and the second resistive circuits through the second external contact. The output circuit has a user mode of operation wherein a supply voltage is applied externally to the first and the second resistive circuits through the second external contact.

Abstract: An array of antennas includes transmitter and receiver circuits. The transmitter includes a digital-to-analog converter (DAC), splitter and filter circuits, and mixer circuits. The DAC circuit converts a digital signal into an analog signal. The splitter and filter circuits separate frequencies of the analog signal into split signals. The mixer circuits multiply frequencies from the split signals by different frequencies of carrier signals to generate modulated signals that are converted into radio frequency (RF) signals. The receiver includes mixer circuits, a summing circuit, and an analog-to-digital converter (ADC). RF signals are converted into electrical signals. The mixer circuits multiply frequencies from the electrical signals with different frequencies of carrier signals. The outputs of the mixer circuits are summed by the summing circuit to generate a summed signal that is converted to digital by the ADC.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: An integrated circuit includes a control circuit configured to send a first command for accessing a row of a memory circuit to the memory circuit during a refresh cycle of the memory circuit. The integrated circuit also includes a first buffer circuit configured to store data accessed from the row of the memory circuit in response to the first command. The integrated circuit also includes a second buffer circuit configured to store an address for the data. The control circuit services a second command for accessing the row during the refresh cycle by accessing the first buffer circuit using the address stored in the second buffer circuit and by preventing the memory circuit from performing an activation command of the row in response to the second command.

Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

Abstract: An integrated circuit includes an output driver circuit having first and second transistors coupled to an external pad of the integrated circuit and first and second multiplexer circuits. The first multiplexer circuit is configurable to cause the first transistor to be controlled by a first voltage during a data output mode of operation and to couple a first control input of the first transistor to the external pad during a hot-socket protection mode of operation. The second multiplexer circuit is configurable to cause the second transistor to be controlled by a second voltage during the data output mode of operation and to couple a second control input of the second transistor to the external pad during the hot-socket protection mode of operation.

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

Abstract: An electronic device includes a first layer and a thermal heatsink that comprises a conductive region in a second layer of the electronic device. The thermal heatsink further comprises a first via that extends through the first layer. The first via is filled with conductive material that is coupled to the conductive region. The conductive material in the first via is coupled to an external terminal of the electronic device. The electronic device can also include a second via filled with conductive material that is coupled to the conductive region.

Abstract: An integrated circuit includes first and second pads, a buffer circuit coupled to the first pad, a first pass gate circuit coupled to the first pad and to the buffer circuit, a second pass gate circuit coupled to the second pad, and a test bus coupled to the first pass gate circuit and the second pass gate circuit. The first pass gate circuit and the second pass gate circuit are configurable to couple the second pad to the buffer circuit through the test bus during a test of the buffer circuit that is performed using the second pad.

Abstract: An electronic device includes conductive pads that are formed on a surface of the electronic device. Each of the conductive pads has an oval shape. The conductive pads are coupled to deliver at least one of a power supply voltage or a ground voltage between an external device and the electronic device.

Abstract: An integrated circuit package includes first and second integrated circuit dies stacked vertically and coupled together, a connection device coupled to the first integrated circuit die, and a power delivery device coupled to the connection device. The power delivery device includes an inductor. The inductor generates supply current. The inductor is coupled to provide the supply current from the inductor to the first integrated circuit die through the connection device.

Abstract: An electronic circuit system includes a main device that generates first and second strobe signals and a clock signal, a first peripheral device that uses the first strobe signal to generate a first output signal in a first lane in response to the clock signal, and a second peripheral device that uses the second strobe signal to generate a second output signal in a second lane in response to the clock signal. The main device determines if the first peripheral device is coupled to the main device through the first lane based on the first output signal. The main device determines if the second peripheral device is coupled to the main device through the second lane based on the second output signal. The main device also has the ability to detect if a peripheral device is faulty and to select a valid configuration of peripheral devices.

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

Abstract: An array of antennas includes transmitter and receiver circuits. The transmitter includes a digital-to-analog converter (DAC), splitter and filter circuits, mixer circuits, and antennas. The DAC circuit converts a digital signal into an analog signal. The splitter and filter circuits separate frequencies of the analog signal into split signals. The mixer circuits multiply frequencies from the split signals by different frequencies of carrier signals to generate modulated signals that are converted by the antennas into radio frequency (RF) signals. The receiver includes antennas, mixer circuits, a summing circuit, and an analog-to-digital converter (ADC). The antennas in the receiver receive RF signals that are converted into electrical signals. The mixer circuits multiply frequencies from the electrical signals with different frequencies of carrier signals. The outputs of the mixer circuits are summed by the summing circuit to generate a summed signal that is converted to digital by the ADC.

Abstract: A method for an audiovisual receiver to request an audiovisual transmitter to reset a communication link includes requesting the reset when the audiovisual receiver determines that the communication link is unlocked. The communication is determined to be unlocked when the active geometry of successive audiovisual frames transmitted from the transmitter to the receiver is determined by the receiver to be inconsistent. The communication is also determined to be unlocked when the interval between control bits of the successive audiovisual frames is inconsistent. When one or both of the inconsistencies is determined, the receiver sets an error bit in a register of the receiver that is accessible by the transmitter to determine from the receiver that the communication link is unlocked.

Abstract: An integrated circuit may include orthogonal multi-phase scheduling circuitry. The scheduling circuitry may include a number of orthogonal scheduling circuits each of which is configured to receive different command types and to output a single winning command. The scheduling circuitry may further include a phase assignment circuit for receiving the winning commands from the orthogonal scheduling circuits and for assigning the received winning commands to different corresponding phase groups. Each orthogonal scheduling circuit may include command buffers, command arbiters, a global arbiter, and associated safe checking circuits.

Abstract: An integrated circuit includes an anti-tamper circuit having a resistor. The resistor includes conductors in a conductive layer of the integrated circuit. Each of the conductors extends across a width of the integrated circuit. The conductors are spaced apart across a length of the integrated circuit. The anti-tamper circuit generates an output signal indicative of changes in a resistance of the resistor caused by tampering that affects the conductors.

Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.