Patents Assigned to Altera Corporation
  • Patent number: 10686446
    Abstract: A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary versions of a user signal. The first and second sets of transistors may be coupled in series between a positive power supply terminal and a ground power supply terminal. A LUT multiplexer implemented in this way need not include separate transmission gates at the output of each tristate inverting circuit and may exhibit minimal subthreshold leakage.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 16, 2020
    Assignee: Altera Corporation
    Inventors: Bee Yee Ng, Hee Kong Phoon, Teik Hong Ooi, Guan Hoe Oh
  • Patent number: 10686449
    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 16, 2020
    Assignee: Altera Corporation
    Inventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
  • Patent number: 10678510
    Abstract: The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the floating-point arithmetic circuitry may be implemented in specialized processing blocks.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 9, 2020
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 10678979
    Abstract: A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 9, 2020
    Assignee: Altera Corporation
    Inventors: Michael David Hutton, Herman Henry Schmit
  • Patent number: 10678715
    Abstract: Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: June 9, 2020
    Assignee: Altera Corporation
    Inventor: Steven Perry
  • Patent number: 10671790
    Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: June 2, 2020
    Assignee: Altera Corporation
    Inventor: Mahesh A. Iyer
  • Patent number: 10671781
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Altera Corporation
    Inventors: Salem Derisavi, Gordon Raymond Chiu, Benjamin Gamsa, David Ian M. Milton
  • Patent number: 10657291
    Abstract: An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the mode of the integrated circuit.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: May 19, 2020
    Assignee: Altera Corporation
    Inventors: Bruce Pedersen, Ting Lu, Brian Wong, Alok Doshi, Yun Sum Wong
  • Patent number: 10649944
    Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 12, 2020
    Assignee: Altera Corporation
    Inventors: Ramanand Venkata, Gopi Krishnamurthy
  • Patent number: 10649731
    Abstract: Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum and difference outputs in parallel. A group of four such specialized processing blocks may be connected in a chain to implement a radix-2 fast Fourier transform (FFT) butterfly. Multiple radix-2 butterflies may be stacked to form yet higher order radix butterflies. If desired, the specialized processing block may also be used to implement a complex multiply operation. Three or four specialized processing blocks may be chained together and along with one or more adders outside the specialized processing blocks, real and imaginary portions of a complex product can be generated.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 12, 2020
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 10635631
    Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 28, 2020
    Assignee: Altera Corporation
    Inventors: Michael D. Hutton, Anargyros Krikelis
  • Patent number: 10635772
    Abstract: A method for designing a system on a target device includes generating a first netlist for a first version of the system after performing synthesis in a first compilation. Optimizations are performed on the first version of the system during placement and routing in the first compilation resulting in a second netlist. A third netlist is generated for a second version of the system after performing synthesis in a second compilation. A hybrid netlist is generated from the first, second, and third netlists. Incremental placement and routing are performed on portions of the hybrid netlist that are new to the first compilation.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: April 28, 2020
    Assignee: Altera Corporation
    Inventors: Junaid Asim Khan, Gabriel Quan, Ketan Padalia, Scott James Brissenden, Ryan Fung
  • Patent number: 10614354
    Abstract: A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to implement a standard convolution layer. A configuration of the CNN accelerator is modified to change a data flow between components on the CNN accelerator. The one or more processing elements is utilized to implement a fully connected layer in response to the change in the data flow.
    Type: Grant
    Filed: February 6, 2016
    Date of Patent: April 7, 2020
    Assignee: Altera Corporation
    Inventors: Utku Aydonat, Gordon Raymond Chiu, Andrew Chaang Ling
  • Patent number: 10615800
    Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: April 7, 2020
    Assignee: Altera Corporation
    Inventors: Doris Tzu Lang Chen, Deshanand Singh
  • Patent number: 10615955
    Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 7, 2020
    Assignee: Altera Corporation
    Inventors: Boon Hong Oh, Chee Seng Tan, Chau Perng Chin
  • Patent number: 10613831
    Abstract: A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of scaled product sum operations and the implementation of Horner's rule.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 7, 2020
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 10606779
    Abstract: A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. The processing nodes may be connected in a hybrid shared-pipelined topology. Each pipeline stage in the hybrid architecture may include a bus switch and at least two shared processing nodes connected to the output of the bus switch. The bus switched may be configured to route an incoming packet to a selected one of the two processing nodes in that pipeline stage or may only route the incoming packet to the active node if the other node is undergoing partial reconfiguration. Configured in this way, the hybrid topology supports partial reconfiguration of the processing nodes without disrupting or limiting the operating frequency of the overall network.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 31, 2020
    Assignee: Altera Corporation
    Inventor: Evan Custodio
  • Patent number: 10599404
    Abstract: A method of compiling program code includes determining if the program code controls a programmable logic device to execute other program code. The program code is a parallel program having a barrier function call for a group of threads. If it is determined that program code is to control the programmable logic device, then the program code is transformed by replacing the barrier function call with control logic inserted into the program code such that the transformed program code remains a parallel program and maintains synchronization among the group of threads. A compiler system that compiles program code with a barrier function call for a group of threads is also described.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: March 24, 2020
    Assignee: Altera Corporation
    Inventors: David Neto, Deshanand Singh, Tomasz Czajkowski, John Stuart Freeman, Tian Yi David Han
  • Patent number: 10592699
    Abstract: Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 17, 2020
    Assignee: Altera Corporation
    Inventor: Bruce B. Pedersen
  • Patent number: 10591544
    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: March 17, 2020
    Assignee: Altera Corporation
    Inventors: Dana How, Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz