Patents Assigned to Altera Corporation
  • Patent number: 11101930
    Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 24, 2021
    Assignee: Altera Corporation
    Inventor: Jeffrey Schulz
  • Patent number: 11093261
    Abstract: A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. The method further includes sending the acceleration request message to a first acceleration interface located at a configurable processing circuit. The first acceleration interface sends the acceleration request message to a first accelerator, and the first accelerator accelerates the task upon receipt of the acceleration request message.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: August 17, 2021
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Kenneth Chong Yin Tan
  • Patent number: 11093672
    Abstract: A method for implementing physical optimizations includes performing physical optimizations on a first reference version of a design, maintaining a computer-readable list of the physical optimizations, and during a subsequent compile for a second version of the design: identifying matching cells, nets, or both between the first reference version of the design and the second version of the design; and restoring at least a subset of the physical optimizations in the second version of the design by reading the computer-readable list of the physical optimizations and applying the subset to a computer-readable description of the second version of the design.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 17, 2021
    Assignee: Altera Corporation
    Inventors: Junaid Asim Khan, Gabriel Quan, Ketan Padalia, Scott James Brissenden, Ryan Fung
  • Patent number: 11074492
    Abstract: A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to perform convolution. A configuration of the CNN accelerator is modified to change filters implemented by the CNN accelerator and to change formatting of output data. The one or more processing elements are utilized to perform one of deconvolution and backpropagation convolution in response to the change in the filters and formatting of the output data.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: July 27, 2021
    Assignee: Altera Corporation
    Inventors: Meghan Lele, Davor Capalija, Andrew Chaang Ling
  • Patent number: 11016742
    Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 25, 2021
    Assignee: Altera Corporation
    Inventors: Alan Baker, Andrew Chaang Ling, Andrei Mihai Hagiescu Miriste
  • Patent number: 10996926
    Abstract: Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: May 4, 2021
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Publication number: 20210104486
    Abstract: A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of the first package where the first die communicates with the second die at a first data rate while the first die communicates with the IC at a second data rate. The first data rate is higher than the second data rate. Methods of forming a multi-access memory system are also disclosed.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 8, 2021
    Applicant: Altera Corporation
    Inventor: Hui LIU
  • Patent number: 10969820
    Abstract: An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: April 6, 2021
    Assignee: Altera Corporation
    Inventor: Mark Bourgeault
  • Patent number: 10970409
    Abstract: Circuits, methods, and apparatus for storing application data, keys, authorization codes, or other information in a volatile memory on an FPGA. A field programmable gate array (FPGA) can include multiple memory blocks and partition those blocks among multiple independent reconfigurable regions. Access to the memory blocks can then be restricted so that only authorized regions have access to particular memory partitions. In addition, each partition can store multiple message authentication codes (MACs) for further controlling access to data in each partition.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 6, 2021
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 10963291
    Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 30, 2021
    Assignee: Altera Corporation
    Inventors: Abdel Hafiz Rabi, Allen Chen, Mark Jonathan Lewis, Jiefan Zhang
  • Patent number: 10963777
    Abstract: A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to implement a standard convolution layer. A configuration of the CNN accelerator is modified to change a data flow between components on the CNN accelerator. The one or more processing elements is utilized to implement a fully connected layer in response to the change in the data flow.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 30, 2021
    Assignee: Altera Corporation
    Inventors: Utku Aydonat, Gordon Raymond Chiu, Andrew Chaang Ling
  • Patent number: 10958411
    Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: March 23, 2021
    Assignee: Altera Corporation
    Inventors: Boon Hong Oh, Chee Seng Tan, Chau Perng Chin
  • Patent number: 10949599
    Abstract: In one embodiment, a computer-implemented method includes performing retiming using a first circuit design to determine one or more variations to the first circuit design, identifying one or more source registers that are involved in one or more unsuccessful retiming moves due to initial conditions conflicts, and recommending, via a graphical user interface, one or more corrective actions to the one or more source registers to avoid the initial conditions conflicts and improve performance of the one or more variations.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: Altera Corporation
    Inventors: Dai Le, Scott James Brissenden
  • Patent number: 10936531
    Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: March 2, 2021
    Assignee: Altera Corporation
    Inventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau
  • Patent number: 10936772
    Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement a logic design on the integrated circuit. The equipment may perform multiple rounds of incremental physical synthesis, incremental timing analysis, and incremental legalization operations. Each round may involve performing multiple different physical synthesis transforms on the design that are individually rejected until transforms that satisfy legality constraints and improve timing for the logic design are found and incorporated into the netlist. The configuration data may then be generated using the netlist. In this way, the logic design may be incrementally altered and verified during the physical synthesis process. This prevents the need for rejecting or accepting an entire batch logic changes to the netlist even when only some of the changes are non-ideal, thus optimizing circuit performance as well as the compile time required to implement the logic design on the integrated circuit.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 2, 2021
    Assignee: Altera Corporation
    Inventors: Mahesh A. Iyer, Robert Walker, Vasudeva M. Kamath
  • Patent number: 10911164
    Abstract: The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is 10 configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: February 2, 2021
    Assignee: Altera Corporation
    Inventors: Neville Carvalho, Tim Tri Hoang, Sergey Shumarayev
  • Patent number: 10909296
    Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 2, 2021
    Assignee: Altera Corporation
    Inventors: Mark Stephen Wheeler, Gordon Raymond Chiu
  • Publication number: 20210021268
    Abstract: A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.
    Type: Application
    Filed: October 2, 2020
    Publication date: January 21, 2021
    Applicant: Altera Corporation
    Inventor: Tony K. Ngai
  • Patent number: 10896890
    Abstract: A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of the first package where the first die communicates with the second die at a first data rate while the first die communicates with the IC at a second data rate. The first data rate is higher than the second data rate. Methods of forming a multi-access memory system are also disclosed.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: January 19, 2021
    Assignee: Altera Corporation
    Inventor: Hui Liu
  • Patent number: 10884964
    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: January 5, 2021
    Assignee: Altera Corporation
    Inventors: Huy Ngo, Keith Duwel, David W. Mendel