Patents Assigned to Altera Corporation
  • Patent number: 11436382
    Abstract: Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 6, 2022
    Assignee: Altera Corporation
    Inventor: Bruce B. Pedersen
  • Patent number: 11381243
    Abstract: Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the bitstreams may be downloaded to the IC, thus increasing usability of the IC as well providing addition revenue streams.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 5, 2022
    Assignee: Altera Corporation
    Inventors: Joshua Walstrom, Mark Bourgeault
  • Patent number: 11334504
    Abstract: Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 17, 2022
    Assignee: Altera Corporation
    Inventor: Steven Perry
  • Patent number: 11303279
    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: April 12, 2022
    Assignee: Altera Corporation
    Inventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
  • Patent number: 11294842
    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 5, 2022
    Assignee: Altera Corporation
    Inventors: Huy Ngo, Keith Duwel, David W. Mendel
  • Patent number: 11287870
    Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: March 29, 2022
    Assignee: Altera Corporation
    Inventors: Shiva Rao, David Munday
  • Patent number: 11281605
    Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 22, 2022
    Assignee: Altera Corporation
    Inventors: Arifur Rahman, Bernhard Friebe
  • Patent number: 11256656
    Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 22, 2022
    Assignee: Altera Corporation
    Inventors: Michael D. Hutton, Anargyros Krikelis
  • Patent number: 11226925
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 18, 2022
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Arifur Rahman
  • Patent number: 11194757
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: December 7, 2021
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Arifur Rahman
  • Patent number: 11169951
    Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: November 9, 2021
    Assignee: Altera Corporation
    Inventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau
  • Patent number: 11171652
    Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: November 9, 2021
    Assignee: Altera Corporation
    Inventors: Doris Tzu Lang Chen, Deshanand Singh
  • Patent number: 11157440
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: October 26, 2021
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Arifur Rahman
  • Patent number: 11137983
    Abstract: Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 5, 2021
    Assignee: Altera Corporation
    Inventors: Keone Streicher, Martin Langhammer, Yi-Wen Lin, Hyun Yi
  • Patent number: 11101930
    Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 24, 2021
    Assignee: Altera Corporation
    Inventor: Jeffrey Schulz
  • Patent number: 11093261
    Abstract: A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. The method further includes sending the acceleration request message to a first acceleration interface located at a configurable processing circuit. The first acceleration interface sends the acceleration request message to a first accelerator, and the first accelerator accelerates the task upon receipt of the acceleration request message.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: August 17, 2021
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Kenneth Chong Yin Tan
  • Patent number: 11093672
    Abstract: A method for implementing physical optimizations includes performing physical optimizations on a first reference version of a design, maintaining a computer-readable list of the physical optimizations, and during a subsequent compile for a second version of the design: identifying matching cells, nets, or both between the first reference version of the design and the second version of the design; and restoring at least a subset of the physical optimizations in the second version of the design by reading the computer-readable list of the physical optimizations and applying the subset to a computer-readable description of the second version of the design.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 17, 2021
    Assignee: Altera Corporation
    Inventors: Junaid Asim Khan, Gabriel Quan, Ketan Padalia, Scott James Brissenden, Ryan Fung
  • Patent number: 11074492
    Abstract: A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to perform convolution. A configuration of the CNN accelerator is modified to change filters implemented by the CNN accelerator and to change formatting of output data. The one or more processing elements are utilized to perform one of deconvolution and backpropagation convolution in response to the change in the filters and formatting of the output data.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: July 27, 2021
    Assignee: Altera Corporation
    Inventors: Meghan Lele, Davor Capalija, Andrew Chaang Ling
  • Patent number: 11016742
    Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 25, 2021
    Assignee: Altera Corporation
    Inventors: Alan Baker, Andrew Chaang Ling, Andrei Mihai Hagiescu Miriste
  • Patent number: 10996926
    Abstract: Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: May 4, 2021
    Assignee: Altera Corporation
    Inventor: Martin Langhammer