Patents Assigned to Altera Corporation
  • Patent number: 10289483
    Abstract: A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: May 14, 2019
    Assignee: Altera Corporation
    Inventors: Herman Henry Schmit, Michael David Hutton
  • Patent number: 10289585
    Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in storage nodes of a pipeline element and the identical routing signal bypassing the pipeline element. A programming element may access the storage nodes of the pipeline elements for write operations and, if desired, for read operations. For example, the programming element may perform write operations to initialize the storage nodes to a known state during power-up operations or to reset the pipeline element. In addition, the programming element may perform reed operations for debug and testing purposes.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: May 14, 2019
    Assignee: Altera Corporation
    Inventor: Jeffrey Christopher Chromczak
  • Patent number: 10291442
    Abstract: Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: May 14, 2019
    Assignee: Altera Corporation
    Inventors: David W. Mendel, Han Hua Leong
  • Patent number: 10282508
    Abstract: In one embodiment, a computer-implemented method includes performing retiming using a first circuit design to determine one or more variations to the first circuit design, identifying one or more source registers that are involved in one or more unsuccessful retiming moves due to initial conditions conflicts, and recommending, via a graphical user interface, one or more corrective actions to the one or more source registers to avoid the initial conditions conflicts and improve performance of the one or more variations.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 7, 2019
    Assignee: Altera Corporation
    Inventors: Dai Le, Scott James Brissenden
  • Patent number: 10282109
    Abstract: An integrated circuit may include memory interface circuitry for communicating with an external or in-package memory module. The integrated circuit may also include out-of-order (OOO) clients and in-order (IO) clients that issue read and write commands to the memory interface circuitry. The memory interface circuitry may include a memory controller having an OOO command scheduler, a write data buffer, and a simple read data pipeline. The memory interface circuitry may also include a multiport arbitration circuit for interfacing with the multiple clients and also OOO adaptor circuits interposed between the multiport arbitration circuit and the IO clients. Each of the OOO adaptor circuits may include an ID generator and a local reordering buffer and may allow the memory controller to return data to the various clients without throttling.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 7, 2019
    Assignee: Altera Corporation
    Inventor: Chee Hak Teh
  • Patent number: 10275557
    Abstract: A method for designing a system on a target device includes identifying portions in the system to preserve based on comparing structural characteristics of the system with another system. Design results from the another system are reused for portions in the system that are preserved.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: April 30, 2019
    Assignee: Altera Corporation
    Inventors: Kevin Chan, Mark Bourgeault
  • Patent number: 10270447
    Abstract: An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened circuitry. The FPGA also includes a configurable interface circuit that is adapted to couple together the two circuits.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 23, 2019
    Assignee: Altera Corporation
    Inventors: Sean R. Atsatt, Kent Orthner, Daniel R. Mansur
  • Patent number: 10268605
    Abstract: Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: April 23, 2019
    Assignee: Altera Corporation
    Inventor: Steven Perry
  • Patent number: 10268392
    Abstract: Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in a third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: April 23, 2019
    Assignee: Altera Corporation
    Inventor: Chee Hak Teh
  • Patent number: 10255404
    Abstract: A computer-implemented includes performing retiming using a circuit design to determine variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes computing and maintaining programmable power-up states for the second set of registers in the variations. The programmable power-up states computed for the second set of registers are equivalent to the defined power-up states of the first set of registers. The method includes identifying registers of the second set of registers involved in an initial state conflict, and performing a mitigating action to resolve the initial state conflict to enable retiming to continue while maintaining functionally equivalent behavior as the circuit design. Various choices of initial states are also explored during retiming to maximize the effect of retiming.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 9, 2019
    Assignee: Altera Corporation
    Inventors: Mahesh A. Iyer, Vasudeva M. Kamath, Robert Lawrence Walker
  • Patent number: 10250347
    Abstract: TDM circuitry that includes a rotary multiplexer and a memory circuit is provided. A first rotary multiplexer circuit may receive N-bit wide data in accordance to a time division multiple access (TDMA) scheme. The N-bit wide data includes multiple sets of M-bit wide data. The first rotary multiplexer may rotate these sets of the M-bit wide data. The memory circuit is coupled to the first rotary multiplexer circuit. The memory circuit stores each of rotated set of M-bit wide data. A second rotary multiplexer circuit may read k-th bits of the each of the stored M-bit wide data from the memory circuit and may rotate these k-th bits before outputting these k-th bits serially, where k is an integer having a value greater than 0.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 2, 2019
    Assignee: ALTERA CORPORATION
    Inventors: Chuck Rumbolt, Stephen Craig
  • Patent number: 10242141
    Abstract: A computer-implemented method includes receiving a first circuit design for an integrated circuit device, determining when multiple power-drawing events are to occur at substantially the same time via one or more circuitry components of the integrated circuit device, which would have a disruptive effect on a power distribution network of the integrated circuit device, based on the first circuit design, and generating logic that schedules the more than one event so that the more than one event do not occur simultaneously. The logic is included in an event sequencer. The method also includes inserting the event sequencer into the first circuit design during compilation to create a second circuit design and outputting the second circuit design to be implemented on the integrated circuit device.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 26, 2019
    Assignee: Altera Corporation
    Inventors: Jakob Raymond Jones, Tim Tri Hoang, Ben Chunben Wang
  • Patent number: 10242146
    Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 26, 2019
    Assignee: Altera Corporation
    Inventors: David Samuel Goldman, Mark Bourgeault, Vaughn Betz, Alan Louis Herrmann
  • Patent number: 10242144
    Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an optimal design on the integrated circuit. Implementing the optimal design may include placing hardware resources within the integrated circuit to decrease or remove overlaps between corresponding hardware resources. A given hardware resource may be defined as a rectangular region, an adjacent hardware resource may be defined as another rectangular region, and together, they may be defined as a hardware resource pair. The hardware resource pair may define an overlap region, with which a cost function may be associated. The cost function may be minimized in conjunction with other types of cost functions using a solver. The solver may generate coordinates that minimize or remove overlap to be implemented in the optimal design.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: March 26, 2019
    Assignee: Altera Corporation
    Inventors: Saurabh Adya, Mahesh A. Iyer, Love Singhal
  • Patent number: 10237066
    Abstract: A scalable and efficient cryptographic architecture is provided for processing data using deeply-pipelined algorithms and circuitries. The architecture can be implemented as circuitry in a fixed logic device, or can be configured into a programmable integrated circuit device. The same top-level design may be used for different choices of data channels, processing depth, parallelism level, and/or system throughput. An encryption pipeline processing block performs rounds of processing upon a block of said data using an encryption process and receives a respective round encryption key for each round of processing. An encryption key pipeline block provides the respective round encryption key for each round of processing by selecting, for each round of processing, the respective round encryption key from at least a first round encryption key corresponding to a first channel and a second round encryption key corresponding to a second channel.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: March 19, 2019
    Assignee: ALTERA CORPORATION
    Inventors: Martin Langhammer, Shawn Nicholl, Cheng Wang
  • Patent number: 10235485
    Abstract: Circuitry for the simulation of partial reconfiguration of a logic design for an integrated circuit device using a hybrid model is provided. The circuitry may create a hybrid model by combining structural model netlists of one or more partial reconfiguration partitions of the logic design with a behavioral model of a static partition of the logic design. The hybrid model may undergo partial reconfiguration verification to ensure that undefined signals do not bypass a freeze bridge and pass from registers in the partial reconfiguration partitions to the static partition, and to ensure that these registers are each in a defined state after the partial reconfiguration operation and a register reset operation are completed.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 19, 2019
    Assignee: Altera Corporation
    Inventors: Mahesh A. Iyer, Kalen B. Brunham
  • Patent number: 10236055
    Abstract: Integrated circuits with memory elements are provided. In particular, a group of random-access memory cells may be coupled to first and second data lines via corresponding access transistors. One of the first and second data lines can be driven to a ground voltage level to write a zero or one into a selected memory cell in the group. A first dummy data line can be formed adjacent to the first data line, whereas a second dummy data line can be formed adjacent to the second data line. During data loading operations, at least one of the dummy data lines can be pulsed to temporarily drive the voltage on the associated data line to below the ground voltage level. Operated in this way, the write operation of the memory cells can be improved.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 19, 2019
    Assignee: Altera Corporation
    Inventors: Rajiv Kumar, Kuan Cheng Tang
  • Patent number: 10236043
    Abstract: Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: March 19, 2019
    Assignee: Altera Corporation
    Inventor: Pohrong Rita Chu
  • Patent number: 10230399
    Abstract: Decoder circuitry for an input channel having a data rate, where a codeword on the input channel includes a plurality of symbols, includes options to provide a first output channel having that data rate, and a plurality of second output channels having slower data rates. The decoder circuitry includes syndrome calculation circuitry, polynomial calculation circuitry, and search-and-correct circuitry. The syndrome calculation circuitry includes finite-field multipliers for multiplying each symbol by a power of a root of the field. Each multiplier other than a first multiplier multiplies a symbol by a higher power of the root than an adjacent multiplier. First-level adders add outputs of a number of groups of multipliers. A second-level adder adds outputs of the first-level adders to be accumulated as syndromes of the first output channel. Another plurality of accumulators accumulates outputs of the first-level adders, which after scaling, are syndromes of the second output channels.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 12, 2019
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 10228415
    Abstract: Test circuitry for providing security in an integrated circuit includes a control circuit and a test power-on-reset circuit. The control circuit determines whether the integrated circuit is configured in a non-secure condition, and that generates a control signal in response to the non-secure condition. Accordingly, the test power-on-reset circuit selectively disables a power-on-reset circuit on the integrated circuit in response the control signal during test operations. The test power-on-reset circuit receives control instructions from the control circuit, and produces a test power-on-reset output according to the control instructions. The integrated circuit includes a logic gate that receives the test power-on-reset output and a power-on-reset signal from the power-on-reset circuit and generates an output signal for bypassing operations of the power-on-reset circuit on the integrated circuit.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 12, 2019
    Assignee: Altera Corporation
    Inventors: Wei Yee Koay, Ting Lu, Ka Bo Wong, Rajiv Kumar