Patents Assigned to Altera Corporation
  • Patent number: 12292752
    Abstract: An electronic system includes first, second, third, and fourth integrated circuit dies. The third integrated circuit die has a first voltage regulator circuit. A supply voltage output of the first voltage regulator circuit is coupled to provide a first supply voltage to a supply voltage input of the first integrated circuit die. The first voltage regulator circuit generates a first power ready signal that indicates when the first supply voltage has reached a first threshold voltage. The fourth integrated circuit die has a second voltage regulator circuit that generates a second supply voltage in response to the first power ready signal. A supply voltage output of the second voltage regulator circuit is coupled to provide the second supply voltage to a supply voltage input of the second integrated circuit die.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 6, 2025
    Assignee: Altera Corporation
    Inventors: Aurelien Mozipo, Archanna Srinivasan, Guang Chen, Janani Chandrasekhar
  • Publication number: 20250130943
    Abstract: An integrated circuit includes a device coherency circuit, first and second traffic generator processor circuits, first and second interfaces, and a processor control finite state machine circuit that causes the first traffic generator processor circuit to perform first coherency data validation for first data sets and that causes the second traffic generator processor circuit to perform second coherency data validation for second data sets. The first traffic generator processor circuit transmits first traffic for the first data sets to the device coherency circuit through the first interface. The second traffic generator processor circuit transmits second traffic for the second data sets to the device coherency circuit through the second interface.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 24, 2025
    Applicant: Altera Corporation
    Inventors: Divya Vijayaraghavan, Joshua Schabel
  • Publication number: 20250123647
    Abstract: An integrated circuit includes a first amplifier circuit coupled to receive a first voltage, a second amplifier circuit coupled to receive the first voltage, and a transistor. The second amplifier circuit is coupled to an output of the first amplifier circuit. An input of the transistor is coupled to an output of the second amplifier circuit. The transistor is coupled to the output of the first amplifier circuit. The second amplifier circuit varies a current through the transistor to the output of the first amplifier circuit based on a difference between the first voltage and a second voltage at the output of the first amplifier circuit to supply leakage current drawn by load circuits.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Applicant: Altera Corporation
    Inventors: Muhammad Yousuf Siddiqui, Maneesha Yellepeddi
  • Patent number: 12278630
    Abstract: A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale/offset block communicatively coupled to the second FFT engine and the scale/offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: April 15, 2025
    Assignee: Altera Corporation
    Inventor: Volker Mauer
  • Publication number: 20250119155
    Abstract: An integrated circuit includes filter circuits that partition a wideband digital signal in a frequency domain to generate narrowband digital signals each having a different frequency band, digital-to-analog converter circuits that convert the narrowband digital signals to generate analog signals, and an analog combiner circuit that combines the analog signals into a single wideband analog signal.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Applicant: Altera Corporation
    Inventor: Dan Pritsker
  • Patent number: 12273282
    Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: April 8, 2025
    Assignee: Altera Corporation
    Inventors: Kevin Clark, Scott J. Weber, Ravi Prakash Gutala, Aravind Raghavendra Dasu
  • Patent number: 12273107
    Abstract: Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: April 8, 2025
    Assignee: Altera Corporation
    Inventors: Atul Maheshwari, Mahesh Iyer, Mahesh K. Kumashikar, Ian Kuon, Yuet Li, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 12265772
    Abstract: Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits that would allow these attacks by other parties. This set of configuration bits that should be excluded for preventing all peek and poke attacks creates the exclusion configuration. Methods are described that disable a particular class of peek and/or poke attacks through the use of partial reconfiguration. Methods and apparatus are described to dynamically detect peek and/or poke attacks.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: April 1, 2025
    Assignee: Altera Corporation
    Inventors: Scott Weber, Sean R. Atsatt, David Goldman
  • Patent number: 12265417
    Abstract: An integrated circuit includes a clock macro circuit. The clock macro circuit includes first, second, and third latch circuits and a multiplexer circuit. The first latch circuit is coupled to the second latch circuit. The multiplexer circuit is coupled to the second and third latch circuits. The clock macro circuit includes programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second latch circuit, the third latch circuit, and the multiplexer circuit. Programming the programmable vias causes the clock macro circuit to function as a selected type of clock circuit.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: April 1, 2025
    Assignee: Altera Corporation
    Inventors: Alexander Rusakov, Alexander Andreev, Eng Huat Lee, Andrei Nikishin
  • Patent number: 12266625
    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: April 1, 2025
    Assignee: Altera Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 12255648
    Abstract: A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: March 18, 2025
    Assignee: Altera Corporation
    Inventors: Archanna Srinivasan, Ravi Gutala, Scott Weber, Aravind Dasu, Mahesh Iyer, Eriko Nurvitadhi
  • Patent number: 12254316
    Abstract: The present disclosure relates to an integrated circuit device that includes a plurality of vector registers configurable to store a plurality of vectors and switch circuitry communicatively coupled to the plurality of vector registers. The switch circuitry is configurable to route a portion of the plurality of vectors. Additionally, the integrated circuit device includes a plurality of vector processing units communicatively coupled to the switch circuitry. The plurality of vector processing units is configurable to receive the portion of the plurality of vectors, perform one or more operations involving the portion of the plurality of vector inputs, and output a second plurality of vectors generated by performing the one or more operations.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: March 18, 2025
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Eriko Nurvitadhi, Gregg William Baeckler
  • Patent number: 12253870
    Abstract: A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 18, 2025
    Assignee: Altera Corporation
    Inventors: Archanna Srinivasan, Ravi Gutala, Scott Weber, Aravind Dasu, Mahesh Iyer, Eriko Nurvitadhi
  • Publication number: 20250087577
    Abstract: An electronic interconnection device includes a guard ring that has a conductive region having a rectangular shape and a via filled with conductive material that is coupled to the conductive region. The guard ring is configured to provide shielding that reduces cross-coupling between inductors that are external to the electronic interconnection device. The via may extend to an external surface of the electronic interconnection device.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Applicant: Altera Corporation
    Inventor: Krishna Bharath Kolluru
  • Patent number: 12249988
    Abstract: An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that has a second comparator circuit that compares the supply voltage to the threshold voltage to generate a second detection signal that indicates the decrease, and a second timestamp storage circuit that stores a second timestamp in response to the second detection signal indicating the decrease. The integrated circuit includes a control circuit that determines a location of a source of the decrease in the integrated circuit based on the first and the second timestamps.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 11, 2025
    Assignee: Altera Corporation
    Inventors: Ping-Chen Liu, Guang Chen, Venu Kondapalli
  • Patent number: 12248021
    Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 11, 2025
    Assignee: Altera Corporation
    Inventors: Sean R. Atsatt, Ilya K. Ganusov
  • Patent number: 12237245
    Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: February 25, 2025
    Assignee: Altera Corporation
    Inventors: Loke Yip Foo, Choong Kooi Chee
  • Publication number: 20250061257
    Abstract: A system includes a hard network-on-chip (NOC) and lookup table random access memory (LUTRAM) circuits usable as logic gates in a user design for an integrated circuit and reprogrammable in a user mode of the integrated circuit through the hard NOC. The LUTRAM circuits are reconfigurable during the user mode of the integrated circuit by providing a bit through the hard NOC for storage in the one of the LUTRAM circuits.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Applicant: Altera Corporation
    Inventors: Bee Yee Ng, Gaik Ming Chan, Sergey Gribok, Scott Weber
  • Patent number: 12216150
    Abstract: A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 4, 2025
    Assignee: Altera Corporation
    Inventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Mahesh A. Iyer, Dhananjay Raghavan
  • Patent number: 12210873
    Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: January 28, 2025
    Assignee: Altera Corporation
    Inventors: Eriko Nurvitadhi, Scott J. Weber, Ravi Prakash Gutala, Aravind Raghavendra Dasu