Abstract: A method of dividing a set of components of an integrated circuit is disclosed. Two or more different security labels are assigned to two or more non-overlapping subsets of the set of components. A handoff file is generated based on the non-overlapping subsets and sent to the integrated circuit. The set of components of the integrated circuit is divided according to the non-overlapping subsets based on the system handoff file.

Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. That compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.

Abstract: Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to “clear,” such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.

Abstract: This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

Abstract: A circuit system includes a current sensor circuit, a subtractor circuit, a multiplier circuit, and a divider circuit. The current sensor circuit generates a current sense signal that indicates a current through an inductor. The circuit system generates a current value based on the current sense signal. The subtractor circuit determines a voltage difference across the inductor. The multiplier circuit multiplies the voltage difference by a time period that the voltage difference is applied across the inductor to generate a product. The divider circuit divides the product by the current value to generate an estimated inductance of the inductor.

Abstract: A flash memory operating circuit in an integrated circuit includes a buffer memory and a speed mode intellectual property (IP) block. The speed mode IP block is communicatively coupled to the buffer memory. The speed mode IP block performs a flash memory operation on a flash memory in the integrated circuit.

Abstract: Systems and methods related to phase-locked loops circuitry and lock-detect circuitry are provided. Some of the systems and methods allow sharing of lock-detect circuitries between multiple phase-locked loops or other suitable circuitry. Others allow multiple circuitries to select from multiple lock-detect circuitries that may use different lock-detect techniques.

Abstract: For an integrated circuit (IC) that is designed to execute user defined operations after initialization, a sequencing circuitry in the IC that delays the start of the user design execution until a set of initial condition has been computed and propagated is provided. The sequencing holds the first group of circuits at an initial state while a second group of circuits computes and propagates a set of initial conditions based at least partly on the initial state of the first group of circuits. The circuits in the first group when being held disregard their inputs and do not change their outputs. The first group of circuits is released from its initial state after the second group of circuits has completed computation and propagation of the set of initial conditions. The circuits in the first group when released are freed to store or clock-in new inputs and produce new outputs in order to perform the user defined operations in conjunction with the second group of circuits.

Abstract: Embodiments of the disclosure relate to systems and methods to reduce power consumption in an integrated circuit (IC) device by controlling various power consuming components of the IC device to a sleep mode when the power consuming components are not in use. The reduction in power consumption by the various power consuming components may reduce power consumption of the IC device in general. In one example, the IC device may include power consuming buffers of data input paths, data output paths, address pin paths, and a clock output path. The IC device may instruct one or more of the power consuming buffers to enter a sleep mode when functions of the one or more power consuming buffers are not in use. In this manner, the IC device may save power while performing various operations (e.g., read/write operations and memory refresh operations).

Abstract: An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.

Abstract: One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment relates to a method of data detection and event capture. Another embodiment relates to an integrated circuit having a first data detection and event capture circuit in a receiver circuit and a second data detection and event capture circuit in a transmitter circuit. Other embodiments and features are also disclosed.

Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

Abstract: A method for designing a system on a target device includes performing speculative register retiming with speculative changes made to a design of the system after an initial compilation of the design. A strategy is generated for an actual register retiming in response to user specified preferences on the speculative changes.

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.

Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.

Abstract: Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.

Abstract: One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.

Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement a logic design on the integrated circuit. The equipment may perform incremental physical synthesis, timing optimization, and legalization operations on the logic design. The equipment may identify timing and legalization constraints and logic blocks that fail the timing constraints, and may determine whether modifying and/or moving the blocks to new locations satisfy the legalization constraints while improving the timing of the design. If the legalization constraints are not satisfied, the design equipment may recursively move non-critical logic blocks to new locations while ensuring that the legalization and timing constraints are satisfied for each move such that the timing of the design is improved. This may be repeated in multiple rounds of adjustment. A netlist may be generated after the moves are performed. The configuration data may be generated based on the netlist.

Abstract: One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency clock generator circuit with a non-divider structure. The local 2× frequency clock generator circuit includes a first circuit path which is selected by multiplexers for a first serialization ratio and may also include a second circuit path which is selected by the multiplexers for a second serialization ratio. Other embodiments and features are also disclosed.