Abstract: An “architecture generation engine” is operative with a CAD system to implement circuits into PLD (programmable logic device) architectures and to evaluate performances of different architectures. The architecture generation engine converts a high level, easily specified description of a PLD architecture into a highly detailed, complete PLD architecture database that can be used by a CAD toolset to map a circuit netlist into a PLD. The architecture generation engine also enables performance evaluation of a wide variety of PLD architectures for given benchmark circuits.

Abstract: An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.

Abstract: An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.

Abstract: The invention consists of a new component called the Architecture Generation Engine added to the CAD system for implementing circuits into PLD architectures and for evaluating performances of different architectures. The Architecture Generation Engine converts a high-level, easily specified description of a PLD architecture into the highly detailed, complete PLD architecture database required by the internals of the CAD toolset in order to map a circuit netlist into the PLD. The Architecture Generation Engine also enables the performance evaluation of a wide variety of PLD architectures for given benchmark circuits.

Abstract: An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.