Abstract: A method for communicating data between network devices is disclosed. A transmission signal is sent over a port of one of the network devices, where the port is in communication with other network devices of the network devices. A data frame is also sent over the port. The transmission signal and the data frame are sent for a fixed byte time period and at least one idle pattern is included with the data frame when a time required to send all data present is less than the fixed byte time period.

Abstract: A network device, which includes a port, a tag generation unit and a flow control module, is provided. The port, which is connected to a network entity, is configured to send and receive a data packet. The tag generation unit is configured to generate a tag based upon the network entity. The tag generation unit is also configured to add the tag to the data packet and to activate the tag. The flow control module is coupled with a buffer, and is configured to control storage of the data packet into the buffer. The flow control module is also coupled with the port, and is configured to control a communication session conducted between the network device and the network entity based upon the tag.

Abstract: A method is provided for testing buffer memory. The method includes a step of testing a buffer memory having a plurality of memory locations including redundant memory locations, to determine if any of the plurality of memory locations are unusable. Next, an address of an unusable memory location of the plurality of memory locations is determined. Next, the address of the unusable memory location is stored. Next, a use of the unusable memory location is prevented based on the stored address of the unusable memory location.

Abstract: Methods and circuits utilizing a two stage adaptation algorithm to determine the optimal code for an equalizer to compensate a received signal is disclosed. In the first stage, a coarse tuning algorithm is used to choose a range of codes based on the amplitude of the received signal. The chosen codes will be used as reference points in the second stage. In the second stage, a fine tuning algorithm is used to select a code in the range of reference codes determined in stage one. The fine tuning algorithm looks to the status of the data lock signal generated by the clock recovery circuit. If the data lock signal does not indicate a lock, the fine tuning algorithm cycles through the range of reference codes. If the data lock signal indicates a lock, then that particular code is continued to be used for the equalizer.

Abstract: A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first expansion bus interface and a second expansion bus interface. The first expansion bus interface is connected to the first expansion port. A second switch has a second memory interface and a second expansion port. The second expansion port is connected to the second expansion bus interface, thereby connecting the first switch to the second switch, wherein the expansion bus allows the first switch to directly access the second memory interface through the second switch and the second switch to directly access the first memory interface through the first switch.

Abstract: A method of flow control management of data packets in a switch. The method has the steps of determining each time data is being written to memory in order to calculate a memory used amount; determining each time data is being freed from memory in order to calculate a memory freed amount; and calculating how much total memory is being used using the memory freed amount and the memory used amount. A comparison is made comparing the total memory being used to a first predetermined threshold. When the first predetermined threshold is reached a first threshold command is issued indicating that the first predetermined threshold has been reached.

Abstract: A system for policing traffic of packet transfer in a hub. The system includes a first circuit and a second circuit and a first data line connecting the first circuit to the second circuit, wherein data is transmitted within and between the first circuit and the second circuit across said first data line. A second data line connects the first circuit to the second circuit, wherein data is transmitted within and between the first circuit and the second circuit across the second data line. A monitor monitors the first data line to determine when an amount of data being transmitted on the first data line within the first circuit has reached a threshold. A blocking mechanism prevents data from being transmitted on the first data line from the first circuit to the second circuit when the amount of data being transmitted on the first data line has reached the threshold.

Abstract: A network device includes a first switch, a second switch, and a CPU. The first and second switches each include a group of ports numbered by a numbering scheme, a rate control logic for performing rate control functions related to switching data packets between the network ports, and a local communications channel for transmitting messages between the group of ports and the rate control logic. Each switch is configured to generate rate control messages based on data packet traffic to its group of ports. The CPU is coupled to the first switch and the second switch and configured to control the first switch and the second switch. A first link port of the first switch is coupled to a second link port of the second switch, and the first link port and the second link port are configured to relay the rate control messages to each other.

Abstract: A network device includes a first switch, a second switch, address resolution logic (ARL), and a CPU. The first and second switch having a groups of ports which are a subset of the plurality of ports and are numbered by a different numbering schemes. The CPU coupled to the first switch and the second switch and configured to control the first switch, the second switch, and the ARL. A first link port of the first group of ports is coupled to a second link port of the second group of ports. The ARL is configured to perform address resolution based on the first and second numbering schemes such that when the first network port a data packet received at the first network port destined for the second network port is directly routed from the first network port to the second network port.

Abstract: A network device having a plurality of ports including address resolution logic (ARl), a first switch, a second switch, and a CPU. The first and second switches include groups of ports which are a subset of the plurality of ports and are numbered by different numbering schemes, rate control logic for performing rate control functions related to switching data packets between the network ports, and local communications channels for transmitting messages between the groups of ports and the rate control logic. The first switch is configured to generate a rate control message and relay the rate control message to the second switch, and the second switch is configured to generate a second rate control message based on the first rate control message, where the second rate control message is different than the first message.

Abstract: A network device having a plurality of ports including address resolution logic (ARL), a first switch, a second switch, and a CPU. The first and second switches include groups of ports which are a subset of the plurality of ports and are numbered by different numbering schemes, rate control logic for performing rate control functions related to switching data packets between the network ports, and local communications channels for transmitting messages between the groups of ports and the rate control logic. The first switch is configured to generate a rate control message and relay the rate control message to the second switch, and a first link port of the first switch is configured to generate a second rate control message based on the first rate control message, relay the second rate control message to the second switch, where the second rate control message is different than the first message.

Abstract: A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The first switch is connected to the first interface of the memory/command bus. The second switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The second switch is connected to the second interface of the memory/command bus.

Abstract: A method for encapsulating and decapsulating information into a data packet being transmitted through a plurality of switches. The method has the steps of receiving a data packet in a first switch for transmission to a second switch and encapsulating information into a field of said data packet so that the information, when encapsulated into the data packet, does not increase the size of the data packet. The method also has the steps of transmitting the data packet having the information encapsulated in the data packet to the second switch and receiving the data packet having the information encapsulated in the data packet in the second switch. The final step is the step of decapsulating the information encapsulated in the data packet.

Abstract: A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.

Abstract: A system for connecting multiple repeaters into a single collision domain comprising a first repeater, a second repeater and a stacking bus. The first repeater has a plurality of network ports. The second repeater also has a plurality of network ports. The stacking bus connects the first repeater and the second repeater and is configured to relay status signals between the first and said second repeaters.

Abstract: Circuits for the restoration of a drooped signal are disclosed. In the asynchronous mode circuit, the drooped signal can be restored by detecting the peak of the positive amplitude and the peak of the negative amplitude and take the difference between the two peaks. This difference signal is fed back the equalizer. In the synchronous mode circuit, the drooped signal is sliced and passed to a regeneration circuit. The regeneration circuit uses reference voltage signals and phase information from the slicer to generate a regenerated signal. The regenerated signal is compared with the equalized signal to generate a difference signal, again fed back to the equalizer. The sliced signal is also fed to a clock recovery circuit which recovers the clock signal embedded in the received signal. The two circuits can be combined to provide an optimal circuit for the restoration of a drooped signal.