Abstract: A tamper detection arrangement for use within an integrated circuit (1), the arrangement comprising: at least one input capacitor (4) having a first capacitance value; a feedback capacitor (5) having a second capacitance value; a sensing arrangement comprising an amplifier circuit having the at least one input capacitor as an input and the at least one feedback capacitor in a feedback loop across the amplifier operable to detect a change in the capacitance values between the at least one input capacitor and the feedback capacitor; and a protective shield to protect a sensitive area (2) of the integrated circuit from tampering, the shield being provided by the at least one input capacitor (4).

Abstract: The present arrangement provides a method of treating an oxidized layer of metal nitride, including oxidizing a layer (2) of metal oxide at the surface of a first layer (1) of nitride of said metal using a plasma of an oxidizing species with an oxidation number that is greater than that of oxygen in order to form a metallic layer (3) of a compound based on said metal; and reducing the metallic layer (3) formed in step i) using a plasma of hydrogen and nitrogen to form a second layer (4) of nitride of said metal.

Abstract: A semiconductor substrate (100) has three doped zones (1), (2) and (3), forming a P-N junction (101), the third zone being located between the first zone and the second zone. The P-N junction of the substrate further has a fourth doped zone (4) having a first portion (4A) in contact with the first zone; and a second portion (4B) in contact with the third zone (3), said second portion (4B) extending in the direction of the second zone (2), and not being in contact with the second zone (2); where the fourth zone (4) being doped with the same type of doping as that of the first zone.

Abstract: An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.

Abstract: A method is provided for fabricating a microelectronic device with programmable memory that includes: i) depositing an intermediate layer of a material having a chalcogenide on a first electrode; ii) irradiating the intermediate layer of step i with ultraviolet radiation; iii) depositing an ionizable metallic layer on the intermediate layer obtained in step ii; iv) diffusing the metal ions originating from the ionizable metallic layer of step iii into the intermediate layer to form a chalcogenide material containing metal ions; and v) depositing a second electrode on the layer of chalcogenide material containing metal ions obtained in step iv to form the microelectronic device.

Abstract: A method of fabricating a programmable memory microelectronic device includes depositing onto a first electrode an intermediate layer of a material having a chalcogenide; depositing an ionizable metallic layer on the intermediate layer; irradiating with ultraviolet radiation the ionizable metallic layer so that metallic ions from the ionizable metallic layer diffuse into the intermediate layer to form a chalcogenide material containing metallic ions, and depositing a second electrode on the layer of chalcogenide material containing metallic ions obtained in the prior step. The second and third steps are repeated at least n times, where n is an integer greater than or equal to 1. The ionizable metallic layer deposited during the second step has a sufficiently small thickness that the metallic ions may be diffused totally during the irradiation (third) step.

Abstract: A method of etching a programmable memory microelectronic device (10) having a substrate covered with at least one of the following layers in succession: a first electrode (2) based on a first metallic element; a layer (4) of chalcogenide doped with a second metallic element; a second electrode (5) based on a third metallic element; a diffusion barrier type electrically-conductive layer (6); and a hard mask (7); is provided. The method includes etching, using an inert gas plasma, at least the hard mask (7), the electrically-conductive layer (6), the second electrode (5) and the chalcogenide layer (4), where the etching step is carried out by cathode sputtering at a temperature strictly less than 150° C., preferably at a temperature of at most 120° C., and particularly preferably at a temperature of at most 100° C.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least partially during provision of the metal.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: A magnetoresistive memory cell has a magnetic stack providing an effective anisotropy field of a storage layer of the magnetic stack during thermal select heating, at least one line providing at least one external magnetic field to the magnetic stack, the effective anisotropy field and the at least one external magnetic field having a non-zero angle relative to one another.

Abstract: According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.

Abstract: Embodiments of the present invention relate generally to integrated circuits, to methods for manufacturing an integrated circuit and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a programmable arrangement. The programmable arrangement includes a substrate having a main processing surface, at least two first electrodes, wherein each of the two first electrodes has a side surface being arranged at a respective angle with regard to the main processing surface, the side surfaces facing one another. The programmable arrangement may further include at least one second electrode and ion conducting material between each of the at least two first electrodes and the at least one second electrode, wherein the at least one second electrode is arranged partially between the side surfaces of the two first electrodes facing one another.

Abstract: A method of manufacturing an integrated circuit including a memory device that includes the following processes: forming a mask layer structure above a composite structure including a resistivity changing layer and an electrode layer disposed above the resistivity changing layer; partially patterning the mask layer structure using a first substance; stopping patterning the mask layer structure before exposing the top surface of the electrode layer; at least partially exposing the top surface of the electrode layer using a second substance, the second substance chemically not reacting with the electrode layer material.

Abstract: A method of fabricating submicron objects that includes the following steps: depositing a void layer on a support, depositing a transfer layer on the void layer, producing the objects in the transfer layer, producing a hard mask on a portion of the transfer layer to delimit a region comprising a portion of the objects, and etching the combination formed by the hard mask, the transfer layer and the void layer to eliminate the hard mask and the portion of the transfer layer in the region and to open up the portion of the void layer under the region so that the objects are suspended, the rate of etching the void layer being greater than the rate of etching the transfer layer and the hard mask.

Abstract: According to one embodiment of the present invention, a memory cell array comprises a plurality of voids, the spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids.

Abstract: A retention test system and method for resistively switching memory devices is disclosed. One embodiment provides a plurality of memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, wherein the system is configured to apply a bias voltage to at least one memory cell of the memory device to be tested.

Abstract: An integrated circuit having a cell arrangement is provided. The cell arrangement may include a memory cell and a reference cell. The memory cell has a first memory cell status and a second memory cell status. The reference cell is set to an intermediate memory cell status between the first memory cell status and the second memory cell status.