Abstract: A tamper detection arrangement for use within an integrated circuit (1), the arrangement comprising: at least one input capacitor (4) having a first capacitance value; a feedback capacitor (5) having a second capacitance value; a sensing arrangement comprising an amplifier circuit having the at least one input capacitor as an input and the at least one feedback capacitor in a feedback loop across the amplifier operable to detect a change in the capacitance values between the at least one input capacitor and the feedback capacitor; and a protective shield to protect a sensitive area (2) of the integrated circuit from tampering, the shield being provided by the at least one input capacitor (4).

Abstract: The present arrangement provides a method of treating an oxidized layer of metal nitride, including oxidizing a layer (2) of metal oxide at the surface of a first layer (1) of nitride of said metal using a plasma of an oxidizing species with an oxidation number that is greater than that of oxygen in order to form a metallic layer (3) of a compound based on said metal; and reducing the metallic layer (3) formed in step i) using a plasma of hydrogen and nitrogen to form a second layer (4) of nitride of said metal.

Abstract: A semiconductor substrate (100) has three doped zones (1), (2) and (3), forming a P-N junction (101), the third zone being located between the first zone and the second zone. The P-N junction of the substrate further has a fourth doped zone (4) having a first portion (4A) in contact with the first zone; and a second portion (4B) in contact with the third zone (3), said second portion (4B) extending in the direction of the second zone (2), and not being in contact with the second zone (2); where the fourth zone (4) being doped with the same type of doping as that of the first zone.

Abstract: A solution includes hydrofluoric acid, an alcohol, and a metallic salt, in which the metal has a redox potential that is positive relative to a hydrogen electrode at 25° C.

Abstract: A method is provided for fabricating a microelectronic device with programmable memory that includes: i) depositing an intermediate layer of a material having a chalcogenide on a first electrode; ii) irradiating the intermediate layer of step i with ultraviolet radiation; iii) depositing an ionizable metallic layer on the intermediate layer obtained in step ii; iv) diffusing the metal ions originating from the ionizable metallic layer of step iii into the intermediate layer to form a chalcogenide material containing metal ions; and v) depositing a second electrode on the layer of chalcogenide material containing metal ions obtained in step iv to form the microelectronic device.

Abstract: A method of etching a programmable memory microelectronic device (10) having a substrate covered with at least one of the following layers in succession: a first electrode (2) based on a first metallic element; a layer (4) of chalcogenide doped with a second metallic element; a second electrode (5) based on a third metallic element; a diffusion barrier type electrically-conductive layer (6); and a hard mask (7); is provided. The method includes etching, using an inert gas plasma, at least the hard mask (7), the electrically-conductive layer (6), the second electrode (5) and the chalcogenide layer (4), where the etching step is carried out by cathode sputtering at a temperature strictly less than 150° C., preferably at a temperature of at most 120° C., and particularly preferably at a temperature of at most 100° C.

Abstract: A method of fabricating a programmable memory microelectronic device includes depositing onto a first electrode an intermediate layer of a material having a chalcogenide; depositing an ionizable metallic layer on the intermediate layer; irradiating with ultraviolet radiation the ionizable metallic layer so that metallic ions from the ionizable metallic layer diffuse into the intermediate layer to form a chalcogenide material containing metallic ions, and depositing a second electrode on the layer of chalcogenide material containing metallic ions obtained in the prior step. The second and third steps are repeated at least n times, where n is an integer greater than or equal to 1. The ionizable metallic layer deposited during the second step has a sufficiently small thickness that the metallic ions may be diffused totally during the irradiation (third) step.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least partially during provision of the metal.

Abstract: A method of fabricating submicron objects that includes the following steps: depositing a void layer on a support, depositing a transfer layer on the void layer, producing the objects in the transfer layer, producing a hard mask on a portion of the transfer layer to delimit a region comprising a portion of the objects, and etching the combination formed by the hard mask, the transfer layer and the void layer to eliminate the hard mask and the portion of the transfer layer in the region and to open up the portion of the void layer under the region so that the objects are suspended, the rate of etching the void layer being greater than the rate of etching the transfer layer and the hard mask.

Abstract: A retention test system and method for resistively switching memory devices is disclosed. One embodiment provides a plurality of memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, wherein the system is configured to apply a bias voltage to at least one memory cell of the memory device to be tested.

Abstract: A retention test system and method for resistively switching memory devices is disclosed. One embodiment provides a plurality of memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, wherein the system is configured to apply a bias voltage to at least one memory cell of the memory device to be tested.

Abstract: A design for a memory array that uses bi-directional write currents and that avoids switched ground connections for memory cells, thereby reducing signal loss and noise problems is described. Positive and negative current sources are provided to supply the bi-directional current that is used to write to a memory cell. These current sources may be selectively connected to bit lines that are electrically connected to the memory cells. Applying a positive current, from the positive current source, through a memory cell writes a “1”, and applying a negative current, from the negative current source, through a memory cell writes a “0”. Use of both a positive and a negative current source enables writing to the memory cells without relying on a switched ground connection to provide bi-directional current. This permits a ground connection of each memory cell to be connected to a fixed ground. An example in which this design is used with a spin injection magneto-resistive random access memory (MRAM) device is shown.

Abstract: A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of the applied current or voltage is determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell.

Abstract: A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-conductive layer; a metallic hard mask disposed on the magnetoresistive junction element; a second non-conductive layer above the first non-conductive layer in regions over the hard mask and a second of the metallic lines; a third non-conductive layer disposed above the hard mask; and a fourth non-conductive layer disposed on the third non-conductive layer. The method further includes partially opening first and second trenches to uncover the second non-conductive layer above the hard mask and second metallic line, respectively; fully opening the first and second trenches to uncover the hard mask and second metallic line, respectively; and filling the first and second trenches with conductive material.

Abstract: A method of forming a magnetoresistive junction in a process of manufacturing a magnetoresistive memory cell includes providing a semiconductor substrate having at least one via contact layer on a main surface thereof, depositing a layered structure of magnetoresistive junction layers on the via contact layer, depositing an etch stop layer on the layered structure of magnetoresistive junction layers, depositing at least one hard mask layer on the etch stop layer, patterning and etching the hard mask layer to create a hard mask, removing of polymer residuals from the hard mask, etching of the etch stop layer, and etching the layered structure of magnetoresistive junction layers to create the magnetoresistive junction. The etching stops at the etch stop layer.

Abstract: Method of fabricating an integrated electronic circuit with programmable resistance cells, which comprises providing a substrate; forming an inert electrode; forming a solid electrolyte on the inert electrode; forming an interlayer on the solid electrolyte, the interlayer comprising an active electrode material and nitrogen; and forming an active electrode on the interlayer, the active electrode comprising the active electrode material.

Abstract: A resistive memory cell random access memory device and method for fabrication.

Abstract: A magnetic memory element comprising a magnetic storage element having at least one magnetic layer made of a magnetic material and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, the magnetic layer having a magnetic anisotropy with its magnetization vector being magnetically coupled to at least one current line, and a magnetic sensor element for sensing the magnetization of the at least one magnetic layer of the magnetic storage element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to the magnetization vector of the at least one magnetic layer of the magnetic storage element, the magnetic sensor element being conductively coupled to the at least one current line.

Abstract: An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free) magnetic regions, where the second magnetic region includes at least two ferromagnetic layers that are antiferromagnetically coupled, wherein a coil surrounds the memory chip for creating a magnetic offset field. Further, a method of writing to an MRAM chip includes bringing the memory cells into an active state exhibiting a reduced switching field before writing thereto and bringing the memory cells into a passive state exhibiting enlarged switching field after writing thereto.