Patents Assigned to Altis Semiconductor SNC
  • Patent number: 7643332
    Abstract: A magnetic random access memory cell includes a free layer structure and a reference layer structure including an anti-ferromagnetic layer structure pinning the magnetization orientation of the reference layer structure, the reference layer structure having a higher magnetic coercivity and being magnetically polarizable bidirectional and parallel to more than one axes by a magnetic field applied during a writing procedure so as to store information in the reference layer structure while heating the anti-ferromagnetic layer structure above its blocking temperature.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: January 5, 2010
    Assignees: Infineon Technologies AG, Altis Semiconductor SNC
    Inventor: Rainer Leuschner
  • Patent number: 7602032
    Abstract: A memory and method of making a memory is disclosed. In one embodiment, the memory includes a cap structure for a magnetoresistive random access memory device including an etch stop layer formed over an upper magnetic layer of a magnetoresistive junction (MTJ/MCJ) layered structure and a hardmask layer formed over said etch stop layer, wherein said etch stop layer is selected from a material such that an etch chemistry used for removing said hardmask layer has selectivity against etching said etch stop layer material. In a method of opening the hardmask layer, an etch process to remove exposed portions of the hardmask layer is implemented, where the etch process terminates on the etch stop layer.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: October 13, 2009
    Assignees: Altis Semiconductor SNC, Infineone Technologies AG
    Inventors: Ulrich Klostermann, Chanro Park, Wolfgang Raberg
  • Patent number: 7315467
    Abstract: The present invention relates to a magnetoresistive hybrid memory cell comprising a first stacked structure comprising a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein said first magnetic region being provided with a fixed first magnetic moment vector and said second magnetic region being provided with a free second magnetic moment vector which is free to be switched between the same and opposite directions with respect to said fixed first magnetic moment vector of said first magnetic region, a second stacked structure being at least partly arranged in a lateral relationship as to said first stacked structure and comprising a third magnetic region being provided with a fixed third magnetic moment vector and said second magnetic region; wherein said first and second structures being arranged in between at least two electrodes in electrical contact therewith.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: January 1, 2008
    Assignees: Infineon Technologies AG, Altis Semiconductor SNC, Centre National de la Recherche Scientifique (CNRS), Universite Paris-SUD
    Inventors: Jacques Miltat, Yoshinobu Nakatani
  • Patent number: 7313043
    Abstract: A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first and a second input terminal. A switching circuit is configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: December 25, 2007
    Assignees: Altis Semiconductor SNC, Infineon Technologies AG
    Inventors: Dietmar Gogl, Daniel Braun
  • Patent number: 7272028
    Abstract: A magnetoresistive memory cell includes N magnetoresistive elements conductively connected in series (where N is an integer greater than or equal to two). The magnetoresistive elements, respectively, are positioned between at least two adjacent conductive lines. At least one of the conductive lines is a partially split conductive line having at least one slit portion encompassing an interconnect running therethrough and connected to at least one adjacent magnetoresistive element.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: September 18, 2007
    Assignees: Infineon Technologies AG, Altis Semiconductor SNC
    Inventor: Ihar Kasko