Abstract: Artificial neuromorphic circuit includes synapse and post-neuron circuits. Synapse circuit includes phase change element and receives first and second pulse signals. Post-neuron circuit includes input, output and integration terminals. Integration terminal is charged to membrane potential according to first pulse signal. Post-neuron circuit further includes first and second control circuits, and first and second delay circuits. First control circuit generates firing signal at output terminal based on membrane potential. Second control circuit generates first control signal based on firing signal. First delay circuit delays firing signal to generate second control signal. Second delay circuit delays second control signal to generate third control signal.

Abstract: Artificial neuromorphic circuit includes synapse and post-neuron circuits. Synapse circuit includes phase change element, first switch having at least three terminals, and second switch. Phase change element includes first and second terminals. First switch includes first, second and control terminals. Second switch includes first, second and control terminals. First switch is configured to receive first pulse signal. Second switch is coupled to phase change element and first switch, and is configured to receive second pulse signal. Post-neuron circuit includes capacitor and input terminal. Input terminal of post-neuron circuit charges capacitor in response to first pulse signal. Post-neuron circuit generates firing signal based on voltage level of capacitor and threshold voltage. Post-neuron circuit generates control signal based on firing signal. Control signal controls turning on of second switch.

Abstract: Artificial neuromorphic circuit includes synapse circuit and post-neuron circuit. Synapse circuit includes phase change element, first switch, and second switch. First switch is coupled to phase change element, and is configured to receive first pulse signal. Second switch is coupled to phase change element. Input terminal of post-neuron circuit is coupled to switch circuit, and input terminal is coupled to phase change element. Input terminal charges capacitor through switch circuit in response to first pulse signal. Post-neuron circuit is configured to generate firing signal based on voltage level at input terminal and threshold voltage, and is further configured to generate first control signal and second control signal based on firing signal. Post-neuron circuit turns off switch circuit according to first control signal. Second control signal is configured to cooperate with second pulse signal to control second switch so as to control a state of phase change element.

Abstract: Artificial neuromorphic circuit includes synapse circuit and post-neuron circuit. Synapse circuit includes phase change element, first switch, and second switch. Phase change element includes first terminal and second terminal. First switch includes first terminal and second terminal. Second switch includes first terminal, second terminal, and control terminal. First switch is configured to receive first pulse signal. Second switch is coupled to phase change element and first switch. Second switch is configured to receive second pulse signal. Post-neuron circuit includes capacitor and input terminal. Input terminal of post-neuron circuit charges capacitor in response to first pulse signal. Post-neuron circuit generates firing signal based on voltage level of capacitor and threshold voltage. Post-neuron circuit generates control signal based on firing signal. Control signal controls turning on of second switch.

Abstract: A mixed mode memory comprises a memory array, a word line decoder, an intermediary circuit and a reading and writing circuit, wherein the word line decoder is electrically coupled to the memory array, and the intermediary circuit is electrically coupled to the memory array and the writing circuit. The memory array comprises mixed mode memory cells with each cell comprising a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line which controls the reading and writing component group to be conducted or not conducted, and electrically coupled to two bit lines which respectively transmit two data signals. The storage circuit generates two reading response signals based on a reading drive signal. The selection circuit controls the storage circuit to operate in a volatile or non-volatile storage mode based on a selection voltage.

Abstract: Disclosed is a memory drive device. The memory drive device comprises a control circuit, a reference voltage generation circuit, and a first switch. The control circuit is used to generate a first signal according to an input signal. The reference voltage generation circuit comprises a reference resistor and is used to generate a reference signal according to the first signal. The first switch is coupled to a memory resistor and is used to generate a drive signal according to the first signal so as to set a resistance value of the memory resistor. When the input signal is decreased and a resistance value of the memory resistor is greater than a resistance value of the reference resistor, the time when the drive signal is decreased is greater than the time when the reference signal is decreased.

Abstract: A memory driving device, comprising a switch, a voltage setting circuit, and a bias control circuit. The switch is coupled to a memory at a node. The voltage setting circuit is coupled to the switch and configured to provide a set signal during a first period to turn on the switch, so as to generate current flowing through the switch to the memory unit. The bias control circuit is respectively coupled to the switch and the node, and, during a second period, continuously provides a bias signal to control the switch so as to adaptively adjust a value of the setting current of the switch. The configuration setting terminal is coupled to the voltage setting circuit and the bias control circuit to control the first and the second period.

Abstract: A mixed mode memory comprises a memory array, a word line decoder, an intermediary circuit and a reading and writing circuit, wherein the word line decoder is electrically coupled to the memory array, and the intermediary circuit is electrically coupled to the memory array and the writing circuit. The memory array comprises mixed mode memory cells with each cell comprising a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line which controls the reading and writing component group to be conducted or not conducted, and electrically coupled to two bit lines which respectively transmit two data signals. The storage circuit generates two reading response signals based on a reading drive signal. The selection circuit controls the storage circuit to operate in a volatile or non-volatile storage mode based on a selection voltage.

Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.

Abstract: A memory device includes a memory array, write drivers and a controller. The memory array includes a plurality of memory units respectively arranged in a plurality of bit lines. The write drivers generate a plurality of write bit signals respectively inputted to the bit lines. The controller provides a voltage mode control signal and a current mode control signal. The controller is electrically coupled to the write drivers. Each of the write drivers generates a respective write bit signal of each of the write drivers according to the voltage mode control signal and the current mode control signal. When each of the memory units is in a set state, the controller outputs the voltage mode control signal and the current mode control signal to the write drivers. When each of the memory units is in a reset state, the controller outputs the voltage mode control signal to the write drivers.

Abstract: A memory device includes a memory array, a bit line driving circuit, a word line driving circuit, a read/write circuit, a controller, and a reference driving circuit. The memory array includes several memory units. The bit line driving circuit is configured to interpret a memory bit address and to drive a bit line. The word line driving circuit is configured to interpret a memory word address and to drive a word line. The read/write circuit is configured to read, set, or reset the memory units. The controller is configured to switch the memory array to work in a single memory unit mode or a dual memory unit mode. The reference driving circuit is configured to drive a reference line, wherein the reference line comprises several reference units, and the reference line and the reference units are located in the memory array.

Abstract: A sensing-amplifier device includes a first input terminal, a second input terminal, a reference unit, and a sense amplifier. The reference unit is configured to provide a reference signal. The switching unit is selectively coupled to the first input terminal, the second input terminal, and a reference unit. The sense amplifier includes two terminals. The two terminals of the sense amplifier are coupled to the first input terminal and the second input terminal respectively by switching of the switching unit so as to operate in a twin memory unit mode, or one terminal of the sense amplifier is coupled to the first input terminal or the second input terminal and the other terminal of the sense amplifier is coupled to the reference unit by switching of the switching unit so as to operate in a single memory unit mode.

Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.

Abstract: A memory device includes first and second memory arrays, first and second bit line driving circuits, first and second word line driving circuits, a read/write circuit, a controller, and first and second reference driving circuits. The first and second memory arrays include several memory units. The first and second bit line driving circuits are configured to interpret a memory bit address and drive a bit line. The first and second word line driver circuits are configured to interpret the memory word address and drive the word line. The read/write circuit is configured to read, set or reset the memory units. The controller is configured to switch the first and second memory arrays to work in a single memory unit mode or a dual memory unit mode. The first and second reference driving circuits are configured to drive reference rows.

Abstract: A memory driving circuit is disclosed herein. The memory driving circuit includes a programmable current source, a reference voltage generation unit and a voltage comparator unit, The programmable current source generates a second current according to a first current. The second current flows into a memory cell, and produces a device voltage at the input of the memory cell. The reference voltage generation unit generates a crystal voltage. The voltage comparator unit compares the device voltage with the crystal voltage and sends out a control signal to control the programmable current source. The first current and the second current are adjusted by the control signal so that the shape of the current pulse of SET operation to the memory cell is well controlled.