Abstract: A system and method for isothermally growing HgCdTe having improved material uniformity and run-to-run repeatability employs a growth solution vessel in which a substrate may be inserted. The growth solution is heated and maintained at a constant temperature while causing Hg to vaporize and rise within the growth solution vessel. A water-cooling jacket causes the Hg to condense and form on the walls of the growth solution vessel. The Hg condensate is directed into a calibrated reservoir. HgCdTe growth continues as the Hg is depleted from the growth solution and fills the reservoir. The reservoir is calibrated to hold the specific amount of Hg condensate corresponding to the desired layer of HgCdTe. The reservoir overflows when full and directs the overflow into the growth solution, causing HgCdTe formation to cease. The volume of the reservoir may be altered to capture more or less Hg condensate, as desired, in order to change the amount of HgCdTe formed on the CdTe substrate.

Abstract: An infrared imaging system having a focal plane array including an array of detector elements and a readout circuit and including nonuniformity correction circuitry on the focal plane array. The individual detector elements correspond to pixels of an infrared scene to be imaged. Offsets in detection signals from each pixel arising from nonuniformities in the individual detector elements in the array are corrected by storing offset correction values for each detector element and using the stored offset values to control correction circuitry as the respective detector element signals are read out. The detector array and readout circuit are preferably formed as a monolithic or hybrid structure and the offset correction is provided on the focal plane array prior to signal amplification and analog to digital conversion.

Abstract: A hybrid infrared focal plane array detector employs a detector layer and transparent substrate bonded to a thin semiconductor readout integrated circuit and thicker readout circuit substrate. The readout circuit is rigidly bonded to the readout substrate to form a composite structure having a thermal coefficient of expansion substantially matching that of the detector portion. The hybrid device may be cooled from room temperature to cryogenic operation temperatures without thermal mismatch structural problems.

Abstract: A hybrid infrared focal plane array detector employs a thinned detector layer and substrate directly bonded to a conventional semiconductor readout integrated circuit substrate. The infrared detector layer and transparent substrate is thinned to a thickness of approximately 25-400.mu. to allow the detector to act like a flexible membrane to elastically respond to thermal mismatch due to differing coefficients of thermal expansion between the detector and semiconductor readout circuit as the hybrid device is cooled from manufacturing at room temperature to cryogenic operation temperatures. By thinning the detector substrate to a desired thickness, essentially unlimited hybrid detector sizes may be obtained. Additionally, the detector layer and substrate may be divided into sub-arrays to provide further resistance to stress induced from thermal mismatch.

Abstract: A massively parallel digital image data processor provides a large number of processing elements arranged in a two-dimensional matrix form. Relative indexed addressing among the processing elements is provided, whereby image data may be easily accessed by and shared among all processing elements. A single-instruction/multiple-data (SIMD) architecture provides instructions to the processing elements in parallel in accordance with specific application programs therefor. The processing elements use triple-ported register files for their internal memory which may input and output data independently and simultaneously. The processing elements are memory-mapped into the address space of the processor's embedded computer to simplify addressing thereof. All image data is inputted and outputted in pixel format. All image data is transferred, stored and processed in bit-serial format.

Abstract: A wafer scale test system for testing redundant integrated circuit dies formed on a semiconductor wafer includes wafer scale test pads formed on the wafer and interchip multiplexor means for directing test signals applied to the wafer scale test pads to the individual integrated circuit dies. The interchip multiplexor means includes an input/output buffer circuit for receiving test signals from the wafer pads and applying the test signals to selected interchip multiplexor lines routed to the individual circuit dies. Readouts from output pads on said integrated circuit dies are routed back through the input/output buffer circuit to the wafer test pads to provide test output signals. Low cross-section connecting means are provided across dicing lanes between the integrated circuit die contact pads and the interchip multiplexor lines to avoid shorting during the dicing operation.

Abstract: A wafer scale test system for testing redundant integrated circuit dies formed on a semiconductor wafer includes wafer scale test pads formed on the wafer and interchip multiplexor means for directing test signals applied to the wafer scale test pads to the individual integrated circuit dies. The interchip multiplexor means includes an input/output buffer circuit for receiving test signals from the wafer pads and applying the test signals to selected interchip multiplexor lines routed to the individual circuit dies. Readouts from output pads on said integrated circuit dies are routed back through the input/output buffer circuit to the wafer test pads to provide test output signals. Low cross-section connecting means are provided across dicing lanes between the integrated circuit die contact pads and the interchip multiplexor lines to avoid shorting during the dicing operation.

Abstract: An improved system and method for annealing indium antimonide ion implanted junctions employing an open-tube benign annealing environment. A furnace having a hollow chamber therein is maintained continuously at a predetermined annealing temperature and wafers of indium antimonide to be annealed are inserted into the chamber through a resealable airlock at one end of the chamber. A source of molten indium saturated with antimony is provided within the chamber to maintain desired partial pressures of indium and antimony within the chamber. Hydrogen gas is continuously flushed through the chamber to purge contaminants and maintain the chamber at a desired slight overpressure over atmospheric. At the conclusion of annealing, the indium antimonide wafer is removed from the chamber into the airlock which is flushed with hydrogen gas. The wafer is allowed to cool to room temperature and removed from the airlock for subsequent processing steps.

Abstract: An infrared imaging system having a focal plane array including an array of detector elements and a readout circuit and including nonuniformity correction circuitry on the focal plane array. The individual detector elements correspond to pixels of an infrared scene to be imaged. Offsets in detection signals from each pixel arising from nonuniformities in the individual detector elements in the array are corrected by storing offset correction values for each detector element and using the stored offset values to control correction circuitry as the respective detector element signals are read out. The detector array and readout circuit are preferably formed as a monolithic or hybrid structure and the offset correction is provided on the focal plane array prior to signal amplification and analog to digital conversion.