Abstract: A multiply-accumulate circuit and methods for using the same are disclosed. In one embodiment, a multiply-accumulate circuit includes a memory configured to store a first set of operands and a second set of operands, where the first set of operands and the second set of operands are cross-multiplied to form a plurality of product pairs, a plurality of computation circuits configured to generate a plurality of charges according to the plurality of product pairs, and an aggregator circuit configured to aggregate the plurality of charges from the plurality of computation circuits to record variations of charges, where the variation of charges represent an aggregated value of the plurality of product pairs.

Abstract: A scalable matrix computation circuit and methods for using the same are disclosed. In one embodiment, a matrix computation circuit includes a plurality of first operand memory configured to store a first set of input operands of the matrix computation circuit, a plurality of second operand memory configured to store a second set of input operands of the matrix computation circuit, where the first and second sets of input operands are programmable by the controller, a plurality of multiplier circuits arranged in a plurality of rows and plurality of columns, where each row receives a corresponding operand from the first set of operands, and each column receives a corresponding operand from the second set of operands, and the each corresponding operand from the each row is used multiple times by the multiplier circuits in that row to perform multiplications controlled by the controller, and a plurality of aggregator circuits configured to store charges produced by the plurality of multiplier circuits.

Abstract: A resistive matrix computation circuit and methods for using the same are disclosed.

Abstract: A circuit for reducing dynamic power in SRAM and methods for using the same are disclosed. In one embodiment, a circuit for reducing dynamic power in SRAM includes a plurality of memory blocks, which includes a plurality memory banks, which in turn includes a plurality bit cells; a set of memory bank signal lines; a set of memory block signal lines shared across the plurality of memory banks in the memory block; a bridge circuit couple between the set of memory bank signal lines and the set of memory block signal lines; a set of sense amplifiers corresponding to the set of memory block signal lines, where the set of sense amplifiers are shared among the plurality of memory banks in the memory block; and a controller configured to control an access of one or more bit cells in the plurality bit cells.

Abstract: A signal communication circuit and methods for using the same are disclosed. In one embodiment, a circuit for signal communication includes a signal line configured to transmit signals, a transmitter circuit configured to drive a transmitted signal onto the signal line, a receiver circuit configured to detect the transmitted signal based on a deviation of a received signal from a reference signal on the signal line, and the receiver circuit is further configured to use the received signal to communicate the transmitted signal.

Abstract: Adjustable integrated circuits and methods for designing the same are provided. In one embodiment, a method of designing an integrated circuit includes determining a plurality of design criteria of the integrated circuit; designing a plurality of circuit blocks of the integrated circuit in accordance with the plurality of design criteria, where one or more circuit blocks in the plurality of circuit blocks include one or more feedback paths; designing a circuit performance monitor, where the circuit performance monitor includes one or more replica feedback paths corresponding to the one or more feedback paths in the one or more circuit blocks, and where the circuit performance monitor is configured to monitor feedback path information of the one or more replica feedback paths; verifying the plurality of circuit blocks and the circuit performance monitor to meet the plurality of design criteria; and producing a verified description of the integrated circuit for manufacturing.

Abstract: A circuit for reducing static power in SRAM and methods for using the same are disclosed. In one embodiment, a circuit for reducing static power in SRAM includes a plurality of memory blocks, where a memory block in the plurality of memory blocks includes a plurality memory banks, where a memory bank in the plurality of memory banks includes a plurality bit cells. The circuit further includes a bias circuit configured to produce a bias voltage to a row of bit cells, where the bias circuit is coupled to a circuit ground terminal of the row of bit cells in the plurality of bit cells, and a controller configured to control the bias circuit to produce a first set of bias settings in an access mode and control the bias circuit to produce a second set of bias settings in a standby mode of the SRAM.

Abstract: Apparatuses and Methods for dynamic adjustment of operating conditions of integrated circuits are provided. The method includes receiving, from a voltage reference module, an operating voltage of the integrated circuit, receiving a reference clock to be used as an operating frequency of the integrated circuit and is distributed to by the plurality of circuit blocks in the integrated circuit, measuring feedback path timing information of one or more circuit blocks in the plurality of circuit blocks, comparing the feedback path timing information of the one or more circuit blocks to the reference clock, determining timing margins of corresponding one or more feedback paths of the one or more circuit blocks based on the comparison, and generating a feedback for adjusting the operating voltage or the operating frequency of the integrated circuit based on the timing margins of the one or more feedback paths of the one or more circuit blocks.