Abstract: A form of symbolic logic gate, referred to as don't.sub.-- care logic, provides a construct that does not have a technology primitive correspondent, and that is useful for carrying valuable additional information to logic synthesis and/or logic optimization processes. Thus, a logic optimization process may proceed more effectively when presented with such don't.sub.-- care information because, e.g. overlapping combinational logic is simplified (but not always eliminated) and dependency (i.e. shared combinational logic) is resolved between the data input and the enable input. The don't.sub.-- care gate is readily generalized, such that it can be applied for any technology primitives that have an enable line input, where there is potential shared combinational logic between the data input (or any inputs) and the enable input. Such category may include technology primitives, such as a latch, a D.sub.-- flip.sub.-- flop, and a tri-state element.

Abstract: An integrated circuit random access memory includes a built in self-test ("BIST") system that has separate address counters and scan registers positioned adjacent each of a plurality of memory blocks. A controller is included as part of the test system for generating test patterns, providing an output that indicates whether the memory blocks have passed the test, and for performing other test control functions. The scan registers can also be alternatively used for testing the memory with external test vectors. The test system is designed into an integrated circuit by providing various database files of test system blocks from which a combination may be made to meet the requirements of various types of memory modules and provide a desired BIST algorithm. In designing such a circuit, the designer specifies certain information, such as the memory type to be used, the BIST algorithm to be implemented, and similar high level information.