Abstract: A method for characterizing in pulse-mode a III-V semiconductor transistor (2) utilizes an associated test bench (1). An RF pre-pulse is applied to the gate (2a) of the transistor (2) with a power level NRF defined according to a first predetermined law of variation so as to fix the charge state of the traps in the transistor (2). Then a first DC pulse and a second DC pulse are applied to the gate (2a) and to the drain (2b) of the transistor (2), respectively. The first DC pulse and the second DC pulse have a first DC level N1 and a second DC level N2, respectively, defined according to a second predetermined law of variation.

Abstract: A method for determining optimal source impedance at the input of a device under testing (DUT) in a measurement bench, includes the steps of calibrating a source pull type bench as a measurement bench, adjusting a load impedance and continuous bias of the DUT, generating an electric power signal by the source and injected in the DUT, acquiring input impedances of the DUT and corresponding gain performances.

Abstract: A method for determining optimal source impedance at the input of a device under testing (DUT) in a measurement bench, includes the steps of calibrating a source pull type bench as a measurement bench, adjusting a load impedance and continuous bias of the DUT, generating an electric power signal by the source and injected in the DUT, acquiring input impedances of the DUT and corresponding gain performances.