Abstract: A system and method for half-rate phase detecting are provided. The method comprises: receiving binary data; dividing the data by two; latching the divided data with a first half-rate clock, creating Q1; latching the divided data with a second half-rate clock, the inverse of the first clock, creating Q2; latching Q1 with the second clock, creating Q3; latching Q2 with the first clock, creating Q4; XORing Q1 and Q2 to create phase signals; and, XORing Q3 and Q4 to create reference signals, corresponding to the phase signals. In some aspects of the method, dividing the stream of data by two introduces a processing delay into the divided data. Then, the method further comprises: in response to the phase and reference signals, phase-locking a voltage controlled oscillator to generate the first and second clocks; delaying the received stream of binary data; and, using the first and second clocks to sample the delayed binary data.

Abstract: A system and method have been provided for prioritizing queued information packets having a variable number of cells. A simultaneous deficit round robin (DRR) analysis occurs in the course of several selection cycles. Each queue has an associated increment value. The packet lengths in each queue are simultaneously compared to an accumulation total in every selection cycle. If all the packets have lengths greater than their corresponding accumulation totals, each accumulation total is incremented and the selection process is repeated. If one of the information packets has a number of cells less than, or equal to its corresponding accumulation total, it is selected. In case multiple information packets are eligible, a variety of selection criteria can be used to break a tie. For example, the eligible information packet with the highest class of service (COS) can be selected. The information packet is completed transferred before another selection process is begun.

Abstract: Drive circuitry to provide a DC bias voltage and a high frequency modulation current to an electroabsorption modulator (EAM), including a high frequency modulation current source, a coupling capacitor, and a first DC lead. The drive circuitry may include termination circuitry. One lead of the high frequency modulation current source is electrically coupled to the first semiconductor type contact of the EAM and the other lead of the high frequency modulation current source is electrically coupled to an AC ground. The coupling capacitor includes a first electrode electrically coupled to the second semiconductor type contact of the EAM, a second electrode electrically coupled to the AC ground, and a dielectric layer between the electrodes. The first DC lead is electrically coupled to the EAM-side capacitor electrode and configured to be coupled to a first DC potential.

Abstract: Drive circuitry to provide a DC bias voltage and a high frequency modulation current to an electroabsorption modulator (EAM), including a high frequency modulation current source, a coupling capacitor, and a first DC lead. The drive circuitry may include termination circuitry. One lead of the high frequency modulation current source is electrically coupled to the first semiconductor type contact of the EAM and the other lead of the high frequency modulation current source is electrically coupled to an AC ground. The coupling capacitor includes a first electrode electrically coupled to the second semiconductor type contact of the EAM, a second electrode electrically coupled to the AC ground, and a dielectric layer between the electrodes. The first DC lead is electrically coupled to the EAM-side capacitor electrode and configured to be coupled to a first DC potential.