Abstract: Disclosed is an electrochemical etching system with localized etching capability. The system allows multiple different porous semiconductor regions to be formed on a single semiconductor wafer. Localized etching is achieved through the use of one or more stationary and/or movable computer-controlled inner containers operating within an outer container. The outer container holds the electrolyte solution and acts as an electrolyte supply source for the inner container(s). The inner container(s) limit the size of the etched region of the semiconductor wafer by confining the electric field. Additionally, the current amount passing through each inner container during the electrochemical etching process can be selectively adjusted to achieve a desired result within the etched region. Localized etching of sub-regions within each etched region can also be achieved through the use of different stationary and/or moveable electrode structures and shields within each inner container.

Abstract: A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer.

Abstract: A method and apparatus for fabricating electrochemical copper interconnections between the component parts of an integrated circuit on a semiconductor device. A cathodic platter is provided that includes contact pins that contact the surface of a semiconductor wafer at predetermined locations during the electrochemical deposition process. The contact pins are arranged on the cathodic platter so that when placed on the surface of the semiconductor wafer the contact pins surround the perimetrical edges of each respective semiconductor device on the semiconductor wafer. Once the semiconductor wafer is properly positioned on the cathodic platter, a copper conductive layer can be electrochemically and uniformly deposited on the surface of the semiconductor device.

Abstract: A method of metallizing a semiconductor chip with copper including an inlaid low dielectric constant layer. The method includes the step of depositing a barrier layer on the surface of the semiconductor chip. Next, a copper seed layer is deposited on the barrier layer, and then the copper seed layer is annealed. Microlithography is then performed on the semiconductor chip to form a plurality of wiring line paths with a patterned photoresist layer. After the wiring line paths are formed a copper conductive layer is electroplated to the surface of the semiconductor chip. Next, the patterned photoresist layer is stripped off of the surface of the semiconductor chip. In addition, portions of the barrier layer and the copper seed layer that were covered by the patterned photoresist layer are also removed. A low dielectric constant layer is then deposited on the semiconductor chip to fill the gaps between the newly created copper conductive lines.

Abstract: A dual-mode baseband controller enables a single integrated circuit to support either In-Phase Quadrature (I-Q) or Non-Return to Zero (NRZ) radio-frequency transmitter architectures for use in second generation (CT2) cordless telephones. A radio frequency (RF) interface circuit controls output signals to support either the I-Q architecture or the NRZ architecture, depending on a MODE control bit received from a controlling integrated circuit. The RF interface circuit comprises an I-Q waveform generator, four multiplexers, two digital-to-analog converters, a buffer, interconnecting circuitry, and a timing controller operating under configurable software control.