Abstract: In MOS logic circuits with a non-complementary circuit structure (for example, dynamic CMOS), a prior art logic gate generated only a single output signal. However, the logic tree often implements multiple functions, with one function being contained within another function. With prior art logic, if two or more of these functions are needed as separate available output signals, they have to be implemented in several separate gates. The present invention utilizes intermediate functions within the logic tree, providing gates having multiple outputs. Therefore, the present invention reduces the replication of circuitry, thus reducing circuit device count. The advantages include reduced integrated circuit chip area, speed improvement, and power savings, due to the reduction of device count and the corresponding reduction in wire lengths and output loading, etc.

Abstract: A highly interconnected analog network is constructed with inter-neurons that account for energy function terms of order greater than two. The network comprises analog amplifiers that are connected with a resistive interconnection matrix which connects each amplifier output to the input of all other amplifiers. The connections embodied in the matrix are achieved with conductances whose values are computed in accordance with the set of problem restrictions, while the cost variables of the problem which are to be minimized are incorporated in the input signals.

Abstract: Automatic determination of the lateral offset between a pair of overlapping vernier patterns (20 and 22) on overlying layers (14 and 15) of a semiconductor wafer (10) is achieved by first capturing the image of the vernier patterns using a television camera (26). The output signal of the television camera is processed by an image acquisition circuit (32) coupled to a computer (34) to determine the intensity of each of a plurality of pixels lying within a strip extending across the image of the vernier patterns. The intensity of each of the pixels is mathematically correlated by the computer (34) with each of a plurality of values corresponding to the intensity of each of a plurality of pixels comprising an image representative of a pair of aligned vernier patterns. The location within the captured image of the maximum of the correlated intensities is then found.